i.MX31: Fix mx31_gpio_mux() function and MUX_-macros.
PATCH 2/2 i.MX31: Fix mx31_gpio_mux() function and MUX_-macros.
Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX contacts instead of only the first 256 ones as is the case prior to this patch.
Add missing MUX_* macros and update board files to use the new macros.
Signed-off-by Magnus Lilja <[email protected]>
---
The i.MX31 Litekit parts has been run on target hardware. The ADS and Phycore have only been compile time tested.
board/imx31_litekit/imx31_litekit.c | 14 +++++++------- board/mx31ads/mx31ads.c | 14 +++++++------- cpu/arm1136/mx31/generic.c | 4 ++-- include/asm-arm/arch-mx31/mx31-regs.h | 32 +++++++++++++++++++++++--------- 4 files changed, 39 insertions(+), 25 deletions(-)
board/imx31_litekit/imx31_litekit.c +7 -7
@@ -53,13 +53,13 @@ int board_init (void)mx31_gpio_mux (MUX_CTS1__UART1_CTS_B );/* SPI2 */ -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SS2 ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SCLK ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SPI_RDY ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_MOSI ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_MISO ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SS0 ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SS1 ); +mx31_gpio_mux (MUX_CSPI2_SS2__CSPI2_SS2_B ); +mx31_gpio_mux (MUX_CSPI2_SCLK__CSPI2_CLK ); +mx31_gpio_mux (MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B ); +mx31_gpio_mux (MUX_CSPI2_MOSI__CSPI2_MOSI ); +mx31_gpio_mux (MUX_CSPI2_MISO__CSPI2_MISO ); +mx31_gpio_mux (MUX_CSPI2_SS0__CSPI2_SS0_B ); +mx31_gpio_mux (MUX_CSPI2_SS1__CSPI2_SS1_B );/* start SPI2 clock */ __REG (CCM_CGR2 ) =__REG (CCM_CGR2 ) | (3 <<4 );
board/mx31ads/mx31ads.c +7 -7
@@ -58,13 +58,13 @@ int board_init (void)mx31_gpio_mux (MUX_CTS1__UART1_CTS_B );/* SPI2 */ -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SS2 ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SCLK ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SPI_RDY ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_MOSI ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_MISO ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SS0 ); -mx31_gpio_mux ((MUX_CTL_FUNC <<8 ) |MUX_CTL_CSPI2_SS1 ); +mx31_gpio_mux (MUX_CSPI2_SS2__CSPI2_SS2_B ); +mx31_gpio_mux (MUX_CSPI2_SCLK__CSPI2_CLK ); +mx31_gpio_mux (MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B ); +mx31_gpio_mux (MUX_CSPI2_MOSI__CSPI2_MOSI ); +mx31_gpio_mux (MUX_CSPI2_MISO__CSPI2_MISO ); +mx31_gpio_mux (MUX_CSPI2_SS0__CSPI2_SS0_B ); +mx31_gpio_mux (MUX_CSPI2_SS1__CSPI2_SS1_B );/* start SPI2 clock */ __REG (CCM_CGR2 ) =__REG (CCM_CGR2 ) | (3 <<4 );
cpu/arm1136/mx31/generic.c +2 -2
@@ -81,12 +81,12 @@ void mx31_gpio_mux(unsigned long mode) {unsigned long reg, shift, tmp; - reg =IOMUXC_BASE + (mode &0xfc ); + reg =IOMUXC_BASE + (mode &0x1fc ); shift = (~mode &0x3 ) *8 ; tmp =__REG (reg); tmp &= ~(0xff << shift); - tmp |= ((mode >>8 ) &0xff ) << shift; + tmp |= ((mode >>MUX_MODE_POS ) &0xff ) << shift;__REG (reg) = tmp; }
include/asm-arm/arch-mx31/mx31-regs.h +23 -9
@@ -126,17 +126,31 @@#define MUX_CTL_CSPI2_SS2 0x87#define MUX_CTL_CSPI2_MOSI 0x8b -/* The modes a specific pin can be in -* these macros can be used in mx31_gpio_mux() and have the form -* MUX_[contact name]__[pin function] +/* +* Helper macros for the MUX_[contact name]__[pin function] macros */ -#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1) -#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1) -#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1) -#define MUX_CTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1) +#define MUX_MODE_POS 9 +#define MUX_CREATE (contact, mode) (((mode) << MUX_MODE_POS) | (contact)) -#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) -#define MUX_CSPI2_MISO__I2C2_SDA ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) +/* +* These macros can be used in mx31_gpio_mux() and have the form +* MUX_[contact name]__[pin function] +*/ +#define MUX_RXD1__UART1_RXD_MUX MUX_CREATE(MUX_CTL_RXD1, MUX_CTL_FUNC) +#define MUX_TXD1__UART1_TXD_MUX MUX_CREATE(MUX_CTL_TXD1, MUX_CTL_FUNC) +#define MUX_RTS1__UART1_RTS_B MUX_CREATE(MUX_CTL_RTS1, MUX_CTL_FUNC) +#define MUX_CTS1__UART1_CTS_B MUX_CREATE(MUX_CTL_CTS1, MUX_CTL_FUNC) + +#define MUX_CSPI2_SS0__CSPI2_SS0_B MUX_CREATE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) +#define MUX_CSPI2_SS1__CSPI2_SS1_B MUX_CREATE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) +#define MUX_CSPI2_SS2__CSPI2_SS2_B MUX_CREATE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) +#define MUX_CSPI2_MOSI__CSPI2_MOSI MUX_CREATE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) +#define MUX_CSPI2_MISO__CSPI2_MISO MUX_CREATE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) +#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B MUX_CREATE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) +#define MUX_CSPI2_SCLK__CSPI2_CLK MUX_CREATE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) + +#define MUX_CSPI2_MOSI__I2C2_SCL MUX_CREATE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) +#define MUX_CSPI2_MISO__I2C2_SDA MUX_CREATE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)/* * Memory regions and CS