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Ignore DEBUGCTL MSRs

PATCH Applied Alexander Graf 3 participants 11 messages Jun 24, 2008 – Jul 22, 2008

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Alexander Graf

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#0 lore raw

PATCH 1/1 Ignore DEBUGCTL MSRs

Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

To support VMX too, I put these in the generic code. Maybe the SVM code could be cleaned up to use generic code too.

Signed-off-by Alexander Graf <[email protected]>
arch/x86/kvm/x86.c +10 -0
index fc0721e..02f8490 100644
@@ -609,6 +609,11 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 		pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
 			__func__, data);
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+	case MSR_IA32_LASTBRANCHFROMIP:
+	case MSR_IA32_LASTBRANCHTOIP:
+	case MSR_IA32_LASTINTFROMIP:
+	case MSR_IA32_LASTINTTOIP:
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_UCODE_WRITE:
 		break;

@@ -705,6 +710,11 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 	case MSR_IA32_MC0_MISC+16:
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_EBL_CR_POWERON:
+	case MSR_IA32_DEBUGCTLMSR:
+	case MSR_IA32_LASTBRANCHFROMIP:
+	case MSR_IA32_LASTBRANCHTOIP:
+	case MSR_IA32_LASTINTFROMIP:
+	case MSR_IA32_LASTINTTOIP:
 		data = 0;
 		break;
 	case MSR_MTRRcap:
#1 lore raw

Hi Alex,

Quoted 7 lines · Alexander Graf

Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

To support VMX too, I put these in the generic code. Maybe the SVM code could be cleaned up to use generic code too.

I would prefer if you put that into the VMX specific code. We can't move the SVM parts of it into generic code because Barcelona has hardware support to virtualize these registers. Therefore SVM don't need that in generic code.

Quoted 32 lines
Signed-off-by Alexander Graf <[email protected]>
arch/x86/kvm/x86.c +10 -0
index fc0721e..02f8490 100644
@@ -609,6 +609,11 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 		pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
 			__func__, data);
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+	case MSR_IA32_LASTBRANCHFROMIP:
+	case MSR_IA32_LASTBRANCHTOIP:
+	case MSR_IA32_LASTINTFROMIP:
+	case MSR_IA32_LASTINTTOIP:
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_UCODE_WRITE:
 		break;

@@ -705,6 +710,11 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 	case MSR_IA32_MC0_MISC+16:
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_EBL_CR_POWERON:
+	case MSR_IA32_DEBUGCTLMSR:
+	case MSR_IA32_LASTBRANCHFROMIP:
+	case MSR_IA32_LASTBRANCHTOIP:
+	case MSR_IA32_LASTINTFROMIP:
+	case MSR_IA32_LASTINTTOIP:
 		data = 0;
 		break;
 	case MSR_MTRRcap:
Signature · 6 lines
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 Research  |              General Partner authorized to represent:
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author
#2 lore raw

Hi Joerg,

Quoted 8 lines · Joerg Roedel

Hi Alex,

Quoted 5 lines · Alexander Graf

Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

Quoted 7 lines
Quoted 2 lines

To support VMX too, I put these in the generic code. Maybe the SVM code could be cleaned up to use generic code too.

I would prefer if you put that into the VMX specific code. We can't move the SVM parts of it into generic code because Barcelona has hardware support to virtualize these registers. Therefore SVM don't need that in generic code.

Hum, I'd actually prefer not to handle this specifically in the VMX code. MSRs should be handled in a generic way if they do not need special treatment from the extension side, as in your case. For example if a third virtualization extension might come to life, I would rather see more things handled in x86.c than in all three targets.

Any objections to this? If not, please apply, as it makes Netware work in KVM.

Alex

Quoted 37 lines
Quoted 36 lines
Signed-off-by Alexander Graf <[email protected]>
arch/x86/kvm/x86.c +5 -0
index fc0721e..02f8490 100644
@@ -609,6 +609,11 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu,  
 u32 msr, u64 data)
 		pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
 			__func__, data);
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+	case MSR_IA32_LASTBRANCHFROMIP:
+	case MSR_IA32_LASTBRANCHTOIP:
+	case MSR_IA32_LASTINTFROMIP:
+	case MSR_IA32_LASTINTTOIP:
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_UCODE_WRITE:

		break;
arch/x86/kvm/x86.c +5 -0
@@ -705,6 +710,11 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu,  
 u32 msr, u64 *pdata)
 	case MSR_IA32_MC0_MISC+16:
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_EBL_CR_POWERON:
+	case MSR_IA32_DEBUGCTLMSR:
+	case MSR_IA32_LASTBRANCHFROMIP:
+	case MSR_IA32_LASTBRANCHTOIP:
+	case MSR_IA32_LASTINTFROMIP:
+	case MSR_IA32_LASTINTTOIP:
 		data = 0;
 		break;

case MSR_MTRRcap:

#3 lore raw
In reply to Joerg Roedel
Quoted 9 lines · Joerg Roedel

Hi Alex,

Quoted 5 lines · Alexander Graf

Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

Quoted 9 lines
Quoted 3 lines

To support VMX too, I put these in the generic code. Maybe the SVM code could be cleaned up to use generic code too.

I would prefer if you put that into the VMX specific code. We can't move the SVM parts of it into generic code because Barcelona has hardware support to virtualize these registers. Therefore SVM don't need that in generic code.

The code path is svm_set_msr -> kvm_set_msr_common, so even if it is in the common code path, you can still override it in svm specific code.

Signature · 2 lines
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
#4 lore raw
In reply to Alexander Graf
Quoted 4 lines · Alexander Graf

Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

To support VMX too, I put these in the generic code. Maybe the SVM code could be cleaned up to use generic code too.

Please add a pr_unimpl() when bits that cause a real processor to do something are set.

Signature · 2 lines
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
author
#5 lore raw
Quoted 7 lines · Avi Kivity
Quoted 4 lines · Alexander Graf

Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

To support VMX too, I put these in the generic code. Maybe the SVM code could be cleaned up to use generic code too.

Please add a pr_unimpl() when bits that cause a real processor to do something are set.

Like this? I also removed the set handlers for the *IP MSRs, as these are read only and made it only handle debug bits, no perfmon bits.

Signed-off-by Alexander Graf <[email protected]>
arch/x86/kvm/x86.c +14 -0
index fc0721e..10f5e95 100644
@@ -609,6 +609,15 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 		pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
 			__func__, data);
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+		if (data > (DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
+			/* Values other than LBR and BTF are vendor-specific,
+			   thus reserved and should throw a #GP */
+			return 1;
+		}
+		pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
+			__func__, data);
+		break;
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_UCODE_WRITE:
 		break;

@@ -705,6 +714,11 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 	case MSR_IA32_MC0_MISC+16:
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_EBL_CR_POWERON:
+	case MSR_IA32_DEBUGCTLMSR:
+	case MSR_IA32_LASTBRANCHFROMIP:
+	case MSR_IA32_LASTBRANCHTOIP:
+	case MSR_IA32_LASTINTFROMIP:
+	case MSR_IA32_LASTINTTOIP:
 		data = 0;
 		break;
 	case MSR_MTRRcap:
#6 lore raw
Quoted 11 lines · Alexander Graf
Quoted 7 lines · Avi Kivity
Quoted 4 lines · Alexander Graf

Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

To support VMX too, I put these in the generic code. Maybe the SVM code could be cleaned up to use generic code too.

Please add a pr_unimpl() when bits that cause a real processor to do something are set.

Like this? I also removed the set handlers for the *IP MSRs, as these are read only and made it only handle debug bits, no perfmon bits.

With a changelog entry.

Quoted 8 lines
Signed-off-by Alexander Graf <[email protected]>
arch/x86/kvm/x86.c +0 -0
index fc0721e..10f5e95 100644

arch/x86/kvm/x86.c int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) · line 618

Quoted 10 lines
arch/x86/kvm/x86.c +6 -0
@@ -609,6 +609,15 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 		pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
 			__func__, data);
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+		if (data > (DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
+			/* Values other than LBR and BTF are vendor-specific,
+			   thus reserved and should throw a #GP */
+			return 1;
+		}

'>' is too clever. '& ~(u64)(...)' is clearer.

Arithmetic and logical ops don't mix well.

arch/x86/kvm/x86.c int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)

Quoted 3 lines
arch/x86/kvm/x86.c +2 -0
+		pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
+			__func__, data);

We can avoid the printout if data == 0, since we support that case fully.

Signature · 1 line
error compiling committee.c: too many arguments to function
author
#7 lore raw
Quoted 8 lines · Avi Kivity
Quoted 7 lines · Alexander Graf
Quoted 6 lines · Avi Kivity
Quoted 4 lines · Alexander Graf

Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

To support VMX too, I put these in the generic code. Maybe the SVM code could be cleaned up to use generic code too.

Quoted 6 lines
Quoted 4 lines
Quoted 1 line

Please add a pr_unimpl() when bits that cause a real processor to do something are set.

Like this? I also removed the set handlers for the *IP MSRs, as these are read only and made it only handle debug bits, no perfmon bits.

With a changelog entry.

ok.

Quoted 6 lines

Review

Quoted 4 lines
(quoted diff) +2 -0
+        pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
+            __func__, data);

We can avoid the printout if data == 0, since we support that case fully.

I was thinking a lot about that. Even though we support data == 0, usually the kernel log output is useful for people trying to find if something is cause a problem. If they see that DEBUGCTL gets set, but won't see it getting unset, they'd get confused IMHO. So the current behavior is on purpose, but if you oppose to that idea, please tell me.

---------------

Netware writes to DEBUGCTL and reads from the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

Writes to DEBUGCTL that are vendor-specific are resembled to behave as if the virtual CPU does not know them.

Signed-off-by Alexander Graf <[email protected]>
arch/x86/kvm/x86.c +14 -0
index fc0721e..10f5e95 100644
@@ -609,6 +609,15 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 		pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
 			__func__, data);
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+		if (data & ~(u64)(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
+			/* Values other than LBR and BTF are vendor-specific,
+			   thus reserved and should throw a #GP */
+			return 1;
+		}
+		pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
+			__func__, data);
+		break;
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_UCODE_WRITE:
 		break;

@@ -705,6 +714,11 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 	case MSR_IA32_MC0_MISC+16:
 	case MSR_IA32_UCODE_REV:
 	case MSR_IA32_EBL_CR_POWERON:
+	case MSR_IA32_DEBUGCTLMSR:
+	case MSR_IA32_LASTBRANCHFROMIP:
+	case MSR_IA32_LASTBRANCHTOIP:
+	case MSR_IA32_LASTINTFROMIP:
+	case MSR_IA32_LASTINTTOIP:
 		data = 0;
 		break;
 	case MSR_MTRRcap:
#8 lore raw
Quoted 10 lines · Alexander Graf
Quoted 6 lines

arch/x86/kvm/x86.c int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) · line 619

Quoted 4 lines
arch/x86/kvm/x86.c +2 -0
+        pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
+            __func__, data);

We can avoid the printout if data == 0, since we support that case fully.

I was thinking a lot about that. Even though we support data == 0, usually the kernel log output is useful for people trying to find if something is cause a problem. If they see that DEBUGCTL gets set, but won't see it getting unset, they'd get confused IMHO. So the current behavior is on purpose, but if you oppose to that idea, please tell me.

Once it gets set, you can expect brokenness. It doesn't matter if it gets unset later. So IMO not printing on data == 0 is best: quiet on the cases we support, and loud on cases we don't. So yes, I'd prefer it changed.

Signature · 1 line
error compiling committee.c: too many arguments to function
author
#9 lore raw
Quoted 6 lines · Avi Kivity
Quoted 5 lines · Alexander Graf
Quoted 5 lines
Quoted 4 lines
(quoted diff) +2 -0
+        pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
+            __func__, data);
Quoted 9 lines
Quoted 5 lines
Quoted 1 line

We can avoid the printout if data == 0, since we support that case fully.

I was thinking a lot about that. Even though we support data == 0, usually the kernel log output is useful for people trying to find if something is cause a problem. If they see that DEBUGCTL gets set, but won't see it getting unset, they'd get confused IMHO. So the current behavior is on purpose, but if you oppose to that idea, please tell me.

Once it gets set, you can expect brokenness. It doesn't matter if it gets unset later. So IMO not printing on data == 0 is best: quiet on the cases we support, and loud on cases we don't. So yes, I'd prefer it changed.

Corrected patch follows...

---

Netware writes to DEBUGCTL and reads from the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

Writes to DEBUGCTL that are vendor-specific are resembled to behave as if the virtual CPU does not know them.

Signed-off-by Alexander Graf <[email protected]>
arch/x86/kvm/x86.c +12 -0
index fc0721e..10f5e95 100644
@@ -609,6 +609,15 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 		pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
 			__func__, data);
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+		if (!data) {
+			/* We support the non-activated case already */
+			break;
+		} else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
+			/* Values other than LBR and BTF are vendor-specific,
+			   thus reserved and should throw a #GP */
+			return 1;
+		}
+		pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
+			__func__, data);
+		break;

case MSR_IA32_UCODE_REV:
case MSR_IA32_UCODE_WRITE:
break;
@@ -705,6 +714,11 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
case MSR_IA32_MC0_MISC+16:
case MSR_IA32_UCODE_REV:
case MSR_IA32_EBL_CR_POWERON:
+ case MSR_IA32_DEBUGCTLMSR:
+ case MSR_IA32_LASTBRANCHFROMIP:
+ case MSR_IA32_LASTBRANCHTOIP:
+ case MSR_IA32_LASTINTFROMIP:
+ case MSR_IA32_LASTINTTOIP:
data = 0;
break;
case MSR_MTRRcap:

Applied
#10 lore raw
Quoted 9 lines · Alexander Graf

Corrected patch follows...

---

Netware writes to DEBUGCTL and reads from the DEBUGCTL and LAST*IP MSRs without further checks and is really confused to receive a #GP during that. To make it happy we should just make them stubs, which is exactly what SVM already does.

Writes to DEBUGCTL that are vendor-specific are resembled to behave as if the virtual CPU does not know them.

Applied, thanks.

Signature · 2 lines
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.