Add MIMC200 board

The MIMC200 board is based on Atmel's NGW100 dev kit, but with an extra 8MByte FLASH and 128KByte FRAM.

RESENT to fix stupid line wrapping !! Sorry.
---

CREDITS                        |    4 ++
MAINTAINERS                    |    4 ++
MAKEALL                        |    1 +
Makefile                       |    3 +
board/atmel/mimc200/Makefile   |   40 +++++++++
board/atmel/mimc200/config.mk  |    3 +
board/atmel/mimc200/eth.c      |   36 ++++++++
board/atmel/mimc200/mimc200.c  |  147 ++++++++++++++++++++++++++++++++
board/atmel/mimc200/u-boot.lds |   73 ++++++++++++++++
cpu/at32ap/at32ap700x/clk.c    |    8 ++++
cpu/at32ap/at32ap700x/gpio.c   |    4 ++
cpu/at32ap/cpu.c               |   14 +++++++
drivers/serial/atmel_usart.c   |   43 +++++++++++++++++++++
include/configs/mimc200.h      |  179 ++++++++++++++++++++++++++++++++++++++++
net/eth.c                      |    4 ++
15 files changed, 563 insertions(+), 0 deletions(-)

index 2b0dab7..5010c78 100644
@@ -217,6 +217,10 @@ H: Rich Ireland

E: r.ireland at computer.org
D: FPGA device configuration driver

+H: Mark Jackson
+E: mpfj at mimc.co.uk
+D: Port to MIMC200 board
+
N: Gary Jennejohn
E: garyj at jennejohn.org, gj at denx.de
D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"

index cbe5c47..d4f6639 100644
@@ -709,6 +709,10 @@ Haavard Skinnemoen <[email protected]>
     ATSTK1006    AT32AP7000
     ATNGW100    AT32AP7000
 
+Mark Jackson <[email protected]>
+
+    MIMC200        AT32AP7000
+

#########################################################################
# SuperH Systems: #
# #

index c1a9c60..cfd376c 100755
@@ -715,6 +715,7 @@ LIST_avr32="        \
     atstk1004    \
     atstk1006    \
     atngw100    \
+    mimc200        \

"

#########################################################################

index 369bbd7..d85867c 100644
@@ -2914,6 +2914,9 @@ atstk1004_config    :    unconfig

atstk1006_config : unconfig

     @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x

+mimc200_config : unconfig
+ @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 atmel at32ap700x
+
#========================================================================
# SH3 (SuperH)
#========================================================================

new file mode 100644
index 0000000..9a794e5
@@ -0,0 +1,3 @@
+TEXT_BASE        = 0x00000000
+PLATFORM_RELFLAGS    += -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS    += --gc-sections

new file mode 100644
index 0000000..4e13399
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Ethernet initialization for the AVR32 Network Gateway
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/memory-map.h>
+
+extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+
+#ifdef CONFIG_CMD_NET
+void mimc200_eth_initialize(bd_t *bi)
+{
+    macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+    macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+}
+#endif

new file mode 100644
index 0000000..1b5c635
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB    := $(obj)lib$(BOARD).a
+
+COBJS    := $(BOARD).o eth.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+    $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

index b3aa034..73b859e 100644
@@ -65,4 +65,12 @@ void clk_init(void)
     /* Use PLL0 as main clock */
     sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));

#endif
+
+#ifdef CONFIG_MIMC200

+    // enable gclk outputs
+    //AVR32_PM.gcctrl[0] = 0x0004; /* LVDS at 10MHz */
+    sm_writel(PM_GCCTRL, 0x00000004);
+    //AVR32_PM.gcctrl[1] = 0x0216; /* Ethernet at 25MHz if PLL running */
+    //sm_writel(PM_GCCTRL + 4, 0x00000216);

+#endif
}

index 56ba2f9..7c6679d 100644
@@ -104,8 +104,10 @@ void gpio_enable_macb0(void)
     gpio_select_periph_A(GPIO_PIN_PC11, 0);    /* RXD2    */
     gpio_select_periph_A(GPIO_PIN_PC12, 0);    /* RXD3    */
     gpio_select_periph_A(GPIO_PIN_PC14, 0);    /* RXCK    */
+#ifndef CONFIG_MIMC200
     gpio_select_periph_A(GPIO_PIN_PC18, 0);    /* SPD    */

#endif
+#endif
}

void gpio_enable_macb1(void)
@@ -129,8 +131,10 @@ void gpio_enable_macb1(void)

     gpio_select_periph_B(GPIO_PIN_PC29, 0);    /* RXD2    */
     gpio_select_periph_B(GPIO_PIN_PC30, 0);    /* RXD3    */
     gpio_select_periph_B(GPIO_PIN_PC24, 0);    /* RXCK    */
+#ifndef CONFIG_MIMC200
     gpio_select_periph_B(GPIO_PIN_PD15, 0);    /* SPD    */

#endif
+#endif
}
#endif

index 0ba8361..8985b68 100644
@@ -56,6 +56,20 @@ int cpu_init(void)
     hsmc3_writel(PULSE0, 0x0b0a0906);
     hsmc3_writel(SETUP0, 0x00010002);
 
+#ifdef CONFIG_MIMC200
+    // setup Data Flash chip select (NCS2)
+    hsmc3_writel(MODE2, 0x20121003);
+    hsmc3_writel(CYCLE2, 0x000a0009);
+    hsmc3_writel(PULSE2, 0x0a060806);
+    hsmc3_writel(SETUP2, 0x00030102);
+
+    // setup FRAM chip select (NCS3)
+    hsmc3_writel(MODE3, 0x10120001);
+    hsmc3_writel(CYCLE3, 0x001e001d);
+    hsmc3_writel(PULSE3, 0x08040704);
+    hsmc3_writel(SETUP3, 0x02050204);
+#endif
+
     clk_init();
 
     /* Update the CPU speed according to the PLL configuration */

index f35b997..9e131c0 100644
@@ -21,6 +21,9 @@

#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/memory-map.h>
+#if defined(CONFIG_MIMC200_DBGLINK)
+#include <asm/arch/gpio.h>
+#endif

#if defined(CONFIG_USART0)

# define USART_ID    0
@@ -73,27 +76,67 @@ int serial_init(void)

void serial_putc(char c)
{
+#if defined(CONFIG_MIMC200_DBGLINK)

+    // only output serial data if DEBUG link connected
+    // this is connected to PIOE_21
+    if (gpio_get_value(GPIO_PIN_PE21) == 0)
+    {
+#endif
+
     if (c == '\n')
         serial_putc('\r');

     while (!(usart3_readl(CSR) & USART3_BIT(TXRDY))) ;
     usart3_writel(THR, c);

+
+#if defined(CONFIG_MIMC200_DBGLINK)
+ }
+#endif
}

void serial_puts(const char *s)
{
+#if defined(CONFIG_MIMC200_DBGLINK)

+    // only output serial data if DEBUG link connected
+    // this is connected to PIOE_21
+    if (gpio_get_value(GPIO_PIN_PE21) == 0)
+    {
+#endif
+
     while (*s)
         serial_putc(*s++);

+
+#if defined(CONFIG_MIMC200_DBGLINK)
+ }
+#endif
}

int serial_getc(void)
{
+#if defined(CONFIG_MIMC200_DBGLINK)

+    // only get serial data if DEBUG link connected
+    // this is connected to PIOE_21
+    if (gpio_get_value(GPIO_PIN_PE21) == 1)
+    {

+ return 0;
+ }
+#endif
+

     while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) ;
     return usart3_readl(RHR);
}

int serial_tstc(void)
{
+#if defined(CONFIG_MIMC200_DBGLINK)

+    // only get serial data if DEBUG link connected
+    // this is connected to PIOE_21
+    if (gpio_get_value(GPIO_PIN_PE21) == 1)
+    {

+ return (1 == 0);
+ }
+#endif
+

     return (usart3_readl(CSR) & USART3_BIT(RXRDY)) != 0;
}

index 38979aa..409756d 100644
@@ -75,6 +75,7 @@ extern int atngw100_eth_initialize(bd_t *);

extern int mcffec_initialize(bd_t*);
extern int mcdmafec_initialize(bd_t*);
extern int at91sam9_eth_initialize(bd_t *);
+extern int mimc200_eth_initialize(bd_t *);

#ifdef CONFIG_API
extern void (*push_packet)(volatile void *, int);
@@ -290,6 +291,9 @@ int eth_initialize(bd_t *bis)

     defined(CONFIG_AT91SAM9263)
     at91sam9_eth_initialize(bis);

#endif
+#if defined(CONFIG_MIMC200)
+ mimc200_eth_initialize(bis);
+#endif

     if (!eth_devices) {
         puts ("No ethernet found.\n");