Core 2 Duo specification v4
PATCH 2/3 Core 2 Duo specification v4
This patch adds a Core 2 Duo CPU to the available CPU types. The CPU definition tries to resemble a real CPU as good as possible, whilst not exposing features qemu does not implement.
The patch also includes some minor additions that Core 2 Duo CPUs have:
- New MSR: MSR_IA32_PERF_STATUS
- CPUID up to level 5 (cache info and mwait)
Signed-off-by Alexander Graf <[email protected]>
target-i386/cpu.h +5 -0
@@ -242,6 +242,8 @@#define MSR_MCG_STATUS 0x17a#define MSR_MCG_CTL 0x17b +#define MSR_IA32_PERF_STATUS 0x198 +#define MSR_PAT 0x277#define MSR_EFER 0xc0000080
@@ -341,6 +343,9 @@#define CPUID_VENDOR_AMD_2 0x69746e65/* "enti" */ #define CPUID_VENDOR_AMD_3 0x444d4163/* "cAMD" */ +#define CPUID_MWAIT_IBE (1 << 1)/* Interrupts can exit capability */ +#define CPUID_MWAIT_EMX (0 << 1)/* enumeration supported */ +#define EXCP00_DIVZ 0#define EXCP01_SSTP 1#define EXCP02_NMI 2
target-i386/helper.c +17 -0
@@ -165,6 +165,23 @@ static x86_def_t x86_defs[] = { .xlevel = 0x8000000A, .model_id = "QEMU Virtual CPU version " QEMU_VERSION, }, + { + .name = "core2duo", +/* original is on level 10 */ + .level = 5, + .family = 6, + .model = 15, + .stepping = 11, +/* the original CPU does have many more features that are not implemented yet */ + .features =PPRO_FEATURES | +CPUID_MTRR |CPUID_CLFLUSH |CPUID_MCA | + CPUID_PSE36, + .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, + .ext2_features = (PPRO_FEATURES &0x0183F3FF ) | + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .xlevel = 0x8000000A, + .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", + }, #endif { .name = "qemu32",
target-i386/op_helper.c +43 -0
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