x86: improve instruction selection/placement for ticket locks
PATCH 1/1 x86: improve instruction selection/placement for ticket locks
Reduce the amount of partial register accesses in the NR_CPUS < 256 case, and slightly weaken resource dependencies in the other case.
Signed-off-by Jan Beulich <[email protected]>
Cc Nick Piggin <[email protected]>
--- include/asm-x86/spinlock.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
include/asm-x86/spinlock.h +7 -7
@@ -21,8 +21,10 @@#ifdef CONFIG_X86_32 # define LOCK_PTR_REG "a" +# define REG_PTR_MODE "k"#else # define LOCK_PTR_REG "D" +# define REG_PTR_MODE "q"#endif #if defined(CONFIG_X86_32) && \
@@ -89,19 +91,17 @@ static __always_inline void __ticket_spi static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock) { -int tmp; -short new; +int tmp, new; - asmvolatile ("movw %2,%w0\n\t" + asmvolatile ("movzwl %2, %0\n\t" "cmpb %h0,%b0\n\t" +"leal 0x100(%" REG_PTR_MODE "0), %1\n\t" "jne 1f\n\t" -"movw %w0,%w1\n\t" -"incb %h1\n\t" "lock ; cmpxchgw %w1,%2\n\t" "1:" "sete %b1\n\t" "movzbl %b1,%0\n\t" - :"=&a" (tmp),"=Q" (new),"+m" (lock->slock) + :"=&a" (tmp),"=&q" (new),"+m" (lock->slock) : :"memory" ,"cc" );
@@ -160,8 +160,8 @@ static __always_inline int __ticket_spin"movl %0,%1\n\t" "roll $16, %0\n\t" "cmpl %0,%1\n\t" +"leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t" "jne 1f\n\t" -"addl $0x00010000, %1\n\t" "lock ; cmpxchgl %1,%2\n\t" "1:" "sete %b1\n\t"