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85xx: Using proper I2C source clock divider for MPC8544

PATCH New Wolfgang Grandegger 2 participants 10 messages Sep 30, 2008 – Oct 14, 2008

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Wolfgang Grandegger

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#0 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM.

Signed-off-by Wolfgang Grandegger <[email protected]>
---
 cpu/mpc85xx/speed.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
cpu/mpc85xx/speed.c +2 -2
Index: u-boot/cpu/mpc85xx/speed.c
===================================================================
@@ -101,9 +101,9 @@ int get_clocks (void)
 	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 	 */
 	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
-		gd->i2c1_clk = sys_info.freqSystemBus / 3;
-	else
 		gd->i2c1_clk = sys_info.freqSystemBus / 2;
+	else
+		gd->i2c1_clk = sys_info.freqSystemBus / 3;
 #else
 	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
 	gd->i2c1_clk = sys_info.freqSystemBus / 2;
#1 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

Quoted 9 lines · Wolfgang Grandegger

Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM.

Signed-off-by Wolfgang Grandegger <[email protected]>

---
cpu/mpc85xx/speed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

can you do me a favor and dump the value of MPC85xx_PORDEVSR2. Also can you tell me what rev 8544 you have.

- k

author
#2 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

Quoted 7 lines · Kumar Gala
Quoted 5 lines · Wolfgang Grandegger

Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM.

Quoted 7 lines
Quoted 4 lines
Signed-off-by Wolfgang Grandegger <[email protected]>

---
cpu/mpc85xx/speed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

can you do me a favor and dump the value of MPC85xx_PORDEVSR2. Also can you tell me what rev 8544 you have.

See below:

pordevsr2 at e00e0014=0x8f00007d

CPU: 8544E, Version: 1.1, (0x803c0111)
Core: E500, Version: 2.2, (0x80210022)
Clock Configuration:

         CPU: 667 MHz, CCB: 334 MHz,
         DDR: 167 MHz (334 MT/s data rate), LBC:  41 MHz
  L1:    D-cache 32 kB enabled
         I-cache 32 kB enabled
  Board: Socrates

Wolfgang.

#3 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

Quoted 24 lines · Wolfgang Grandegger
Quoted 8 lines · Kumar Gala
Quoted 6 lines · Wolfgang Grandegger

Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM.

Quoted 7 lines
Quoted 4 lines
Signed-off-by Wolfgang Grandegger <[email protected]>

---
cpu/mpc85xx/speed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

can you do me a favor and dump the value of MPC85xx_PORDEVSR2. Also can you tell me what rev 8544 you have.

See below:

pordevsr2 at e00e0014=0x8f00007d

CPU: 8544E, Version: 1.1, (0x803c0111)
Core: E500, Version: 2.2, (0x80210022)
Clock Configuration:

Quoted 7 lines
        CPU: 667 MHz, CCB: 334 MHz,
        DDR: 167 MHz (334 MT/s data rate), LBC:  41 MHz
 L1:    D-cache 32 kB enabled
        I-cache 32 kB enabled
 Board: Socrates

Wolfgang.

thanks. How did you do the measurements that got you this 1.5x factor?

- k

author
#4 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

Quoted 30 lines · Kumar Gala
Quoted 28 lines · Wolfgang Grandegger
Quoted 8 lines · Kumar Gala
Quoted 6 lines · Wolfgang Grandegger

Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM.

Quoted 6 lines
Quoted 4 lines
Signed-off-by Wolfgang Grandegger <[email protected]>

---
cpu/mpc85xx/speed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

can you do me a favor and dump the value of MPC85xx_PORDEVSR2. Also can you tell me what rev 8544 you have.

See below:

pordevsr2 at e00e0014=0x8f00007d

CPU: 8544E, Version: 1.1, (0x803c0111)
Core: E500, Version: 2.2, (0x80210022)
Clock Configuration:

        CPU: 667 MHz, CCB: 334 MHz,
        DDR: 167 MHz (334 MT/s data rate), LBC:  41 MHz
 L1:    D-cache 32 kB enabled
        I-cache 32 kB enabled
 Board: Socrates
Quoted 3 lines
Quoted 1 line

Wolfgang.

thanks. How did you do the measurements that got you this 1.5x factor?

Actually, this problem was reported by a customer using the I2C bus on the MPC8544E intensively. I'm going to find out how he did the measurements.

Wolfgang.

#6 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

In reply to Wolfgang Grandegger
Quoted 34 lines · Wolfgang Grandegger
Quoted 33 lines · Kumar Gala
Quoted 30 lines · Wolfgang Grandegger
Quoted 8 lines · Kumar Gala
Quoted 6 lines · Wolfgang Grandegger

Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM.

Quoted 7 lines
Quoted 4 lines
Signed-off-by Wolfgang Grandegger <[email protected]>

---
cpu/mpc85xx/speed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

can you do me a favor and dump the value of MPC85xx_PORDEVSR2. Also
can you tell me what rev 8544 you have.

See below:

pordevsr2 at e00e0014=0x8f00007d

CPU:   8544E, Version: 1.1, (0x803c0111)
Core:  E500, Version: 2.2, (0x80210022)
Clock Configuration:
       CPU: 667 MHz, CCB: 334 MHz,
       DDR: 167 MHz (334 MT/s data rate), LBC:  41 MHz

L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: Socrates

Wolfgang.

Quoted 8 lines
Quoted 2 lines

thanks. How did you do the measurements that got you this 1.5x factor?

This afternoon I re-measured the I2C bus clock frequency with the oscilloscope at the I2C clock line on our Socrates MPC8544 board. With the patch applied, I measured the correct frequency of 100 kHz. Without,
it was a factor of 1.5 too high.

are you able to change cfg_seq_freq on the board?

- k

author
#5 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

In reply to Kumar Gala
Quoted 30 lines · Kumar Gala
Quoted 28 lines · Wolfgang Grandegger
Quoted 8 lines · Kumar Gala
Quoted 6 lines · Wolfgang Grandegger

Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM.

Quoted 6 lines
Quoted 4 lines
Signed-off-by Wolfgang Grandegger <[email protected]>

---
cpu/mpc85xx/speed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

can you do me a favor and dump the value of MPC85xx_PORDEVSR2. Also can you tell me what rev 8544 you have.

See below:

pordevsr2 at e00e0014=0x8f00007d

CPU: 8544E, Version: 1.1, (0x803c0111)
Core: E500, Version: 2.2, (0x80210022)
Clock Configuration:

        CPU: 667 MHz, CCB: 334 MHz,
        DDR: 167 MHz (334 MT/s data rate), LBC:  41 MHz
 L1:    D-cache 32 kB enabled
        I-cache 32 kB enabled
 Board: Socrates
Quoted 3 lines
Quoted 1 line

Wolfgang.

thanks. How did you do the measurements that got you this 1.5x factor?

This afternoon I re-measured the I2C bus clock frequency with the oscilloscope at the I2C clock line on our Socrates MPC8544 board. With the patch applied, I measured the correct frequency of 100 kHz. Without, it was a factor of 1.5 too high.

Wolfgang.

author
#7 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

In reply to Kumar Gala
Quoted 36 lines · Kumar Gala
Quoted 33 lines · Wolfgang Grandegger
Quoted 32 lines · Kumar Gala
Quoted 29 lines · Wolfgang Grandegger
Quoted 8 lines · Kumar Gala
Quoted 6 lines · Wolfgang Grandegger

Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM.

Quoted 6 lines
Quoted 4 lines
Signed-off-by Wolfgang Grandegger <[email protected]>

---
cpu/mpc85xx/speed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

can you do me a favor and dump the value of MPC85xx_PORDEVSR2. Also can you tell me what rev 8544 you have.

See below:

pordevsr2 at e00e0014=0x8f00007d

CPU:   8544E, Version: 1.1, (0x803c0111)
Core:  E500, Version: 2.2, (0x80210022)
Clock Configuration:
       CPU: 667 MHz, CCB: 334 MHz,
       DDR: 167 MHz (334 MT/s data rate), LBC:  41 MHz

L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: Socrates

Wolfgang.

Quoted 8 lines
Quoted 6 lines
Quoted 1 line

thanks. How did you do the measurements that got you this 1.5x factor?

This afternoon I re-measured the I2C bus clock frequency with the oscilloscope at the I2C clock line on our Socrates MPC8544 board. With the patch applied, I measured the correct frequency of 100 kHz. Without, it was a factor of 1.5 too high.

are you able to change cfg_seq_freq on the board?

At least I don't know how. It's defined via hardware strap, I imagine.

Wolfgang.

#8 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

Quoted 10 lines
Quoted 10 lines
Quoted 9 lines
Quoted 2 lines

thanks. How did you do the measurements that got you this 1.5x factor?

This afternoon I re-measured the I2C bus clock frequency with the oscilloscope at the I2C clock line on our Socrates MPC8544 board. With
the patch applied, I measured the correct frequency of 100 kHz. Without,
it was a factor of 1.5 too high.

Quoted 3 lines
Quoted 1 line

are you able to change cfg_seq_freq on the board?

At least I don't know how. It's defined via hardware strap, I imagine.

Its is.. not sure if you have schematics for the board. If you do look to see if LWE_B is wired to anything.

- k

author
#9 lore raw

PATCH 1/1 85xx: Using proper I2C source clock divider for MPC8544

Quoted 8 lines · Kumar Gala
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 2 lines

thanks. How did you do the measurements that got you this 1.5x factor?

This afternoon I re-measured the I2C bus clock frequency with the oscilloscope at the I2C clock line on our Socrates MPC8544 board. With
the patch applied, I measured the correct frequency of 100 kHz. Without,
it was a factor of 1.5 too high.

Quoted 5 lines
Quoted 2 lines
Quoted 1 line

are you able to change cfg_seq_freq on the board?

At least I don't know how. It's defined via hardware strap, I imagine.

Its is.. not sure if you have schematics for the board. If you do look to see if LWE_B is wired to anything.

I'm going to ask the customer. But even if it's wired, the bit in the cfg_sec_freq register should reflect properly that case.

Wolfgang.