x86: Fix conditions for Virtual Wire IRQ delivery
PATCH 1/1 x86: Fix conditions for Virtual Wire IRQ delivery
QEMU is implementing the Virtual Wire mode to attach the PIC to modern, APIC-supporting CPUs. But Intel's MP spec says that PIC interrupts then flow through the APICs, thus they also have to be enabled. Patch below fixes the test logic accordingly, avoiding delivery in case an APIC is disabled.
--- hw/apic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
hw/apic.c +1 -1
@@ -526,7 +526,7 @@ int apic_accept_pic_intr(CPUState *env) lvt0 = s->lvt[APIC_LVT_LINT0 ]; -if ((s->apicbase &MSR_IA32_APICBASE_ENABLE ) ==0 || +if ((s->apicbase &MSR_IA32_APICBASE_ENABLE ) && (lvt0 &APIC_LVT_MASKED ) ==0 )return 1 ;
Signature · 2 lines
Siemens AG, Corporate Technology, CT SE 2 Corporate Competence Center Embedded Linux
Quoted 16 lines · Jan Kiszka
QEMU is implementing the Virtual Wire mode to attach the PIC to modern, APIC-supporting CPUs. But Intel's MP spec says that PIC interrupts then flow through the APICs, thus they also have to be enabled. Patch below fixes the test logic accordingly, avoiding delivery in case an APIC is disabled.
Signed-off-by Jan Kiszka <[email protected]>--- hw/apic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)Index:
b/hw/apic.c
===================================================================
hw/apic.c int apic_accept_pic_intr(CPUState *env) · line 532
Quoted 8 lines
hw/apic.c +1
-1@@ -526,7 +526,7 @@ int apic_accept_pic_intr(CPUState *env) lvt0 = s->lvt[APIC_LVT_LINT0 ]; -if ((s->apicbase &MSR_IA32_APICBASE_ENABLE ) ==0 || +if ((s->apicbase &MSR_IA32_APICBASE_ENABLE ) && (lvt0 &APIC_LVT_MASKED ) ==0 )return 1 ;
This patch turned out to be incorrect (SDM 3A, 5.3.1), please ignore it.
Jan
Signature · 2 lines
Siemens AG, Corporate Technology, CT SE 2 Corporate Competence Center Embedded Linux