intel_txt: Intel(R) TXT boot support
RFC PATCH v6 1/4 intel_txt: Intel(R) TXT boot support
This patch adds kernel configuration and boot support for Intel(R) Trusted Execution Technology (Intel(R) TXT).
Intel's technology for safer computing, Intel(R) Trusted Execution Technology (Intel(R) TXT), defines platform-level enhancements that provide the building blocks for creating trusted platforms.
Intel TXT was formerly known by the code name LaGrande Technology (LT).
Intel TXT in Brief:
o Provides dynamic root of trust for measurement (DRTM) o Data protection in case of improper shutdown o Measurement and verification of launched environment
Intel TXT is part of the vPro(TM) brand and is also available some non-vPro systems. It is currently available on desktop systems based on the Q35, X38, Q45, and Q43 Express chipsets (e.g. Dell Optiplex 755, HP dc7800, etc.) and mobile systems based on the GM45, PM45, and GS45 Express chipsets.
For more information, see http://www.intel.com/technology/security/.
This site also has a link to the Intel TXT MLE Developers Manual, which has been updated for the new released platforms.
A much more complete description of how these patches support TXT, how to configure a system for it, etc. is in the Documentation/intel_txt.txt file in this patch.
This patch provides the TXT support routines for complete functionality, documentation for TXT support and for the changes to the boot_params structure, and boot detection of a TXT launch. Attempts to shutdown (reboot, Sx) the system will result in platform resets; subsequent patches will support these shutdown modes properly.
Documentation/intel_txt.txt | 210 +++++++++++++++++++++ Documentation/x86/zero-page.txt | 1 arch/x86/include/asm/bootparam.h | 3 arch/x86/include/asm/fixmap.h | 3 arch/x86/include/asm/tboot.h | 197 ++++++++++++++++++++ arch/x86/kernel/Makefile | 1 arch/x86/kernel/setup.c | 4 arch/x86/kernel/tboot.c | 379 +++++++++++++++++++++++++++++++++++++++ security/Kconfig | 30 +++ 9 files changed, 827 insertions(+), 1 deletion(-)
---
arch/x86/include/asm/bootparam.h +2 -1
@@ -85,7 +85,8 @@ struct efi_info {struct boot_params {struct screen_info screen_info;/* 0x000 */ struct apm_bios_info apm_bios_info;/* 0x040 */ -__u8 _pad2[12 ];/* 0x054 */ +__u8 _pad2[4 ];/* 0x054 */ +__u64 tboot_addr;/* 0x058 */ struct ist_info ist_info;/* 0x060 */ __u8 _pad3[16 ];/* 0x070 */ __u8 hd0_info[16 ];/* obsolete! */ /* 0x080 */
arch/x86/include/asm/fixmap.h +3 -0
@@ -132,6 +132,9 @@ enum fixed_addresses {#ifdef CONFIG_X86_32 FIX_WP_TEST,#endif +#ifdef CONFIG_INTEL_TXT +FIX_TBOOT_BASE , +#endif __end_of_fixed_addresses };
arch/x86/include/asm/tboot.h +197 -0
197 lines not on this page · raw message
arch/x86/kernel/Makefile +1 -0
@@ -50,6 +50,7 @@ obj-$(CONFIG_X86_DS_SELFTEST) += ds_sel obj-$(CONFIG_X86_32) += tls.o obj-$(CONFIG_IA32_EMULATION) += tls.o obj-y += step.o +obj-$(CONFIG_INTEL_TXT) += tboot.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-y += cpu/ obj-y += acpi/
arch/x86/kernel/setup.c +4 -0
@@ -145,6 +145,8 @@ struct boot_params __initdata boot_paramstruct boot_params boot_params;#endif +#include <asm/tboot.h> +/* * Machine setup.. */
@@ -964,6 +966,8 @@ void __init setup_arch(char **cmdline_p)paravirt_pagetable_setup_done (swapper_pg_dir);paravirt_post_allocator_init (); +tboot_probe (); +#ifdef CONFIG_X86_64 map_vsyscall ();#endif
arch/x86/kernel/tboot.c +379 -0
379 lines not on this page · raw message
Documentation/intel_txt.txt +210 -0
210 lines not on this page · raw message
Documentation/x86/zero-page.txt +1 -0
@@ -12,6 +12,7 @@ Offset Proto Name Meaning 000/040 ALL screen_info Text mode or frame buffer information (struct screen_info) 040/014 ALL apm_bios_info APM BIOS information (struct apm_bios_info) +058/008 ALL tboot_addr Physical address of tboot shared page 060/010 ALL ist_info Intel SpeedStep (IST) BIOS support information (struct ist_info) 080/010 ALL hd0_info hd0 disk parameter, OBSOLETE!!
security/Kconfig +30 -0
@@ -113,6 +113,36 @@ config SECURITY_ROOTPLUG If you are unsure how to answer this question, answer N. +config INTEL_TXT + bool "Enable Intel(R) Trusted Execution Technology (Intel(R) TXT)" + depends on EXPERIMENTAL && X86 && DMAR && ACPI + help + This option enables support for booting the kernel with the + Trusted Boot (tboot) module. This will utilize + Intel(R) Trusted Execution Technology to perform a measured launch + of the kernel. If the system does not support Intel(R) TXT, this + will have no effect. + + Intel TXT will provide higher assurance of sysem configuration and + initial state as well as data reset protection. This is used to + create a robust initial kernel measurement and verification, which + helps to ensure that kernel security mechanisms are functioning + correctly. This level of protection requires a root of trust outside + of the kernel itself. + + Intel TXT also helps solve real end user concerns about having + confidence that their hardware is running the VMM or kernel that + it was conigured with, especially since they may be responsible for + providing such assurances to VMs and services running on it. + + See <http://www.intel.com/technology/security/> for more information + about Intel(R) TXT. + See <http://tboot.sourceforge.net> for more information about tboot. + See Documentation/intel_txt.txt for a description of how to enable + Intel TXT support in a kernel boot. + + If you are unsure as to whether this is required, answer N. + source security/selinux/Kconfig source security/smack/Kconfig source security/tomoyo/Kconfig
Quoted 7 lines · Joseph Cihula
arch/x86/kernel/tboot.c +6
-0+int tboot_force_iommu (void ) +{ +if (!tboot_enabled ()) +return 0 ; + +if (no_iommu || swiotlb || dmar_disabled)
arch/x86/kernel/tboot.c line 379
Quoted 10 lines
arch/x86/kernel/tboot.c +10
-0+pr_warning ("Forcing Intel-IOMMU to enabled\n" ); + + dmar_disabled =0 ; +#ifdef CONFIG_SWIOTLB + swiotlb =0 ; +#endif + no_iommu =0 ; + +return 1 ; +}
Ick. The logic for selecting which IOMMU is used is convoluted enough already, without adding this here.
Signature · 2 lines
David Woodhouse Open Source Technology Centre [email protected] Intel Corporation