ISP OMAP3 camera support ov7690

DISCUSSION michael 2 participants 10 messages Oct 3, 2009 – Jan 13, 2010 1 message not in the archive Media (V4L/DVB)

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michael

author

2009-10-03 23:16 UTC #0 lore raw

Hi all,

I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:

- datalane configuration
- phyconfiguration

How can I map this parameter to a camera? Can anyone give me some example?

Michael

A message that is not in the archive (sent off-list or not yet received): [email protected]

michael

author

2009-10-05 00:31 UTC #2 lore raw

Hi,

cc linux-media

Quoted 7 lines · Nishanth Menon

michael said the following on 10/03/2009 06:13 PM:
Quoted 4 lines
I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:
- datalane configuration
CSI2 Data lanes - each CSI2 lane is a differential pair. And, at least 1 clock and data lane is used in devices.

Sorry can you explain a little bit more. I have the camera connected to the cam_hs and cam_vs and the data is 8Bit. I use the the isp init structure. The sccb bus works great and I can send configuration to it, but I don't receive any interrupt from the ics, seems that it doen't see the transaction:

The ISPCCDC: ###CCDC SYN_MODE=0x31704 seems ok.

static struct isp_interface_config ov7690_if_config = {
       .ccdc_par_ser           = ISP_CSIA,
       .dataline_shift         = 0x0,
       .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSFALL,
       .strobe                 = 0x0,
       .prestrobe              = 0x0,
       .shutter                = 0x0,
       .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
       .wait_hs_vs             = 0x4,
       .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
       .u.csi.crc              = 0x0,
       .u.csi.mode             = 0x0,
       .u.csi.edge             = 0x0,
       .u.csi.signalling       = 0x0,
       .u.csi.strobe_clock_inv = 0x0,
       .u.csi.vs_edge          = 0x0,
       .u.csi.channel          = 0x0,
       .u.csi.vpclk            = 0x1,
       .u.csi.data_start       = 0x0,
       .u.csi.data_size        = 0x0,
       .u.csi.format           = V4L2_PIX_FMT_YUYV,
};

and I don't know the meaning of

lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY;
lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE;
lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY;
lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE;
lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY;
lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE;
lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0;

Quoted 3 lines

Quoted 1 line
- phyconfiguration
PHY - Physical timing configurations. btw, if it is camera specific you could get a lot of inputs from [1].

Ok I wil ask to them.

Quoted 11 lines

Regards,
Nishanth Menon
Ref:
[1] http://vger.kernel.org/vger-lists.html#linux-media
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Michael

Aguirre Rodriguez, Sergio Alberto

2009-10-05 22:23 UTC #3 lore raw

Hi Michael,

Quoted 31 lines

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of michael
Sent: Sunday, October 04, 2009 7:29 PM
To: Nishanth Menon
Cc: [email protected]; [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Hi,
cc linux-media
Quoted 6 lines · Nishanth Menon
michael said the following on 10/03/2009 06:13 PM:
Quoted 4 lines
I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:
- datalane configuration
CSI2 Data lanes - each CSI2 lane is a differential pair.
And, at least 1
Quoted 1 line
clock and data lane is used in devices.
Sorry can you explain a little bit more. I have the camera connected to the
cam_hs and cam_vs and the data is 8Bit. I use the the isp init structure. The sccb bus works great and I can send configuration to it,
but I don't receive any interrupt from the ics, seems that it doen't see
the transaction:

Quoted 7 lines

The ISPCCDC: ###CCDC SYN_MODE=0x31704 seems ok.
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSFALL,

Can you try with ISPCTRL_SYNC_DETECT_VSRISE ?

Quoted 21 lines

        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};

and I don't know the meaning of

Quoted 11 lines

lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY;
lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE;
lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY;
lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE;
lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY;
lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE;
lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0;

This is the physical connection details:

- The .pol field stands for the differntial pair polarity. (i.e. the order in which the negative and positive connections are pugged in to the CSI2 ComplexIO module)

- The .pos field is for telling in which position of the 4 available physically you have your clock, or data lane located.

Regards,
Sergio

Quoted 28 lines

Quoted 2 lines
Quoted 1 line
- phyconfiguration
PHY - Physical timing configurations. btw, if it is camera
specific you
Quoted 1 line
could get a lot of inputs from [1].
Ok I wil ask to them.
Quoted 8 lines
Regards,
Nishanth Menon
Ref:
[1] http://vger.kernel.org/vger-lists.html#linux-media
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Quoted 3 lines
the body of a message to [email protected]
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Michael
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michael

author

2009-10-05 22:35 UTC #4 lore raw

Hi,

Quoted 31 lines · Sergio Alberto

Hi Michael,
Quoted 29 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of michael
Sent: Sunday, October 04, 2009 7:29 PM
To: Nishanth Menon
Cc: [email protected]; [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Hi,
cc linux-media
Quoted 6 lines · Nishanth Menon
michael said the following on 10/03/2009 06:13 PM:
Quoted 4 lines
I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:
- datalane configuration
CSI2 Data lanes - each CSI2 lane is a differential pair.
And, at least 1
Quoted 1 line
clock and data lane is used in devices.
Sorry can you explain a little bit more. I have the camera connected to the cam_hs and cam_vs and the data is 8Bit. I use the the isp init structure. The sccb bus works great and I can send configuration to it, but I don't receive any interrupt from the ics, seems that it doen't see the transaction:
The ISPCCDC: ###CCDC SYN_MODE=0x31704 seems ok.

Quoted 6 lines

Quoted 4 lines
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSFALL,
Can you try with ISPCTRL_SYNC_DETECT_VSRISE ?

I just try to invert the polary and I have no problem to share the code with the community.
The documentation miss info about the 4 clock and 8 clock before and after the frame.
I have the limitation that the camera is always on, so in the POWER_DOWN condidion
I reset it to have the output and signal in HZ state. I think that is correct,
Now I will try to take a look to the logic, because that receive interrupt must be
normal when I put out the signal connection. I can send the patch set to the mailing
linux-media to share the code and maybe there is somenthing else working on the same
device. Do you thing that is is a good idea. There are a lot of work to do for setting
varius control and I don't have a perfect knolowment of the OMAP part. I try to read the code, but I suspect tha I can have basically two problem:

- missend register setting (so I don't enable correcly the signal output
- or somenthing regarding the timing.

The documentation lack and it's incomplete about timing and setting and I'm under nda but the code is offcorse gpl and I have the intention to submit to review or help people like me that are working around the same issue.

Quoted 34 lines

Quoted 22 lines
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
and I don't know the meaning of
Quoted 11 lines
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY;
lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE;
lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY;
lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE;
lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY;
lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE;
lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0;

Quoted 8 lines

This is the physical connection details:
- The .pol field stands for the differntial pair polarity. (i.e. the order in which the negative and positive connections are pugged in to the CSI2 ComplexIO module)
- The .pos field is for telling in which position of the 4 available physically you have your clock, or data lane located.

Ok, so if I don't receive the clock for a wrong routing I can't read the data but I can receive interumpt for vsync falling or rising transaction. Is it correct?

Quoted 3 lines

Regards,
Sergio

Thank's for your time
Regards Michael

Quoted 25 lines

Quoted 25 lines
Quoted 3 lines
Quoted 2 lines
- phyconfiguration
PHY - Physical timing configurations. btw, if it is camera
specific you
Quoted 1 line
could get a lot of inputs from [1].
Ok I wil ask to them.
Quoted 7 lines
Regards,
Nishanth Menon
Ref:
[1] http://vger.kernel.org/vger-lists.html#linux-media
--
To unsubscribe from this list: send the line "unsubscribe
linux-omap" in
Quoted 3 lines
the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Michael
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Michael Trimarchi

author

2010-01-12 13:15 UTC #5 lore raw

In reply to Aguirre Rodriguez, Sergio Alberto

Hi all,

Now I have a good camera pcb and I can test again the driver. My board is an overo gumstix board.

Quoted 71 lines · Sergio Alberto

Hi Michael,
Quoted 26 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of michael
Sent: Sunday, October 04, 2009 7:29 PM
To: Nishanth Menon
Cc: [email protected]; [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Hi,
cc linux-media
Quoted 6 lines · Nishanth Menon
michael said the following on 10/03/2009 06:13 PM:
Quoted 4 lines
I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:
- datalane configuration
CSI2 Data lanes - each CSI2 lane is a differential pair.
And, at least 1
Quoted 1 line
clock and data lane is used in devices.
Sorry can you explain a little bit more. I have the camera connected to the cam_hs and cam_vs and the data is 8Bit. I use the the isp init structure. The sccb bus works great and I can send configuration to it, but I don't receive any interrupt from the ics, seems that it doen't see the transaction:
Quoted 7 lines
The ISPCCDC: ###CCDC SYN_MODE=0x31704 seems ok.
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSFALL,
Can you try with ISPCTRL_SYNC_DETECT_VSRISE ?
Quoted 21 lines
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
and I don't know the meaning of
Quoted 11 lines
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY;
lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE;
lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY;
lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE;
lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY;
lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE;
lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0;

Quoted 5 lines

This is the physical connection details:
- The .pol field stands for the differntial pair polarity. (i.e. the order in which the negative and positive connections are pugged in to the CSI2 ComplexIO module)

What exact the meaning of the pol, sorry? I have a signal that is connected
to a pin. If the pos is avalaible can I use it? It's not important how to route the signal but don't route on the same lane. Is it right?

This is the timing of the camera so I can check signal, but I don't receive interrupt of isp engine

Quoted 1 line

The camera is direct connected to the camera omap camera signal and using the oscilloscope I can see the hs/vs signal The hs is low and go up, like the vs signal. I have only one camera
with that use D0 to D7 data bit.

http://www.gumstix.net/Hardware/view/I/O-connectors-cabling/Gumstix-Overo-27-pin-connector-J5-to-manage-camera-controls/112.html

static struct isp_interface_config ov7690_if_config = {
       .ccdc_par_ser           = ISP_CSIA,
       .dataline_shift         = 0x0,
       .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSRISE,
       .strobe                 = 0x0,
       .prestrobe              = 0x0,
       .shutter                = 0x0,
       .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
       .wait_hs_vs             = 0x4,
       .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
       .u.csi.crc              = 0x0,
       .u.csi.mode             = 0x0,
       .u.csi.edge             = 0x0,
       .u.csi.signalling       = 0x0,
       .u.csi.strobe_clock_inv = 0x0,
       .u.csi.vs_edge          = 0x0,
       .u.csi.channel          = 0x0,
       .u.csi.vpclk            = 0x1,
       .u.csi.data_start       = 0x0,
       .u.csi.data_size        = 0x0,
       .u.csi.format           = V4L2_PIX_FMT_YUYV,
};

This is my initial configuration

#define OV7690_CSI2_CLOCK_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA0_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA1_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_CLOCK_LANE          1        /* Clock lane position: 1 */
#define OV7690_CSI2_DATA0_LANE          2        /* Data0 lane position: 2 */
#define OV7690_CSI2_DATA1_LANE          3        /* Data1 lane position: 3 */
tim#define OV7690_CSI2_PHY_THS_TERM        2
#define OV7690_CSI2_PHY_THS_SETTLE      23
#define OV7690_CSI2_PHY_TCLK_TERM       0
#define OV7690_CSI2_PHY_TCLK_MISS       1
#define OV7690_CSI2_PHY_TCLK_SETTLE     14

With this clock polarity

lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY; lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE; lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY; lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE; lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY; lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE; lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0; isp_csi2_complexio_lanes_config(&isp->isp_csi2, &lanecfg);

Michael

Aguirre, Sergio

2010-01-12 16:36 UTC #6 lore raw

Quoted 10 lines

-----Original Message-----
From: Michael Trimarchi [mailto:[email protected]]
Sent: Tuesday, January 12, 2010 7:15 AM
To: Aguirre, Sergio
Cc: Nishanth Menon; [email protected]; linux- [email protected]
Subject: Re: ISP OMAP3 camera support ov7690

Quoted 4 lines

Hi all,
Now I have a good camera pcb and I can test again the driver. My board is an overo gumstix board.

Excellent!

Please let me know if you're having issues with it.

Thanks for your interest!

Regards,
Sergio

Quoted 159 lines

Quoted 75 lines · Sergio Alberto
Hi Michael,
Quoted 30 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of michael
Sent: Sunday, October 04, 2009 7:29 PM
To: Nishanth Menon
Cc: [email protected]; [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Hi,
cc linux-media
Quoted 6 lines · Nishanth Menon
michael said the following on 10/03/2009 06:13 PM:
Quoted 4 lines
I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:
- datalane configuration
CSI2 Data lanes - each CSI2 lane is a differential pair.
And, at least 1
Quoted 1 line
clock and data lane is used in devices.
Sorry can you explain a little bit more. I have the camera connected to the
cam_hs and cam_vs and the data is 8Bit. I use the the isp init structure. The sccb bus works great and I can send configuration to it,
but I don't receive any interrupt from the ics, seems that it doen't see
the transaction:
Quoted 7 lines
The ISPCCDC: ###CCDC SYN_MODE=0x31704 seems ok.
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSFALL,
Can you try with ISPCTRL_SYNC_DETECT_VSRISE ?
Quoted 21 lines
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
and I don't know the meaning of
Quoted 11 lines
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY;
lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE;
lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY;
lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE;
lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY;
lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE;
lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0;
Quoted 5 lines
This is the physical connection details:
- The .pol field stands for the differntial pair polarity. (i.e. the order in which the negative and positive connections are pugged in to the CSI2 ComplexIO module)
What exact the meaning of the pol, sorry? I have a signal that is connected
to a pin. If the pos is avalaible can I use it?
It's not important how to route the signal but don't route on the same lane.
Is it right?
This is the timing of the camera so I can check signal, but I don't receive interrupt
of isp engine
Quoted 1 line
The camera is direct connected to the
camera omap camera signal and using the oscilloscope I can see the hs/vs signal
The hs is low and go up, like the vs signal. I have only one camera with that use D0 to D7 data bit.
http://www.gumstix.net/Hardware/view/I/O-connectors-cabling/Gumstix-Overo-
27-pin-connector-J5-to-manage-camera-controls/112.html
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSRISE,
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
This is my initial configuration
#define OV7690_CSI2_CLOCK_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA0_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA1_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_CLOCK_LANE          1        /* Clock lane position: 1
*/
#define OV7690_CSI2_DATA0_LANE 2 /* Data0 lane position: 2
*/
#define OV7690_CSI2_DATA1_LANE 3 /* Data1 lane position: 3
*/
tim#define OV7690_CSI2_PHY_THS_TERM 2
#define OV7690_CSI2_PHY_THS_SETTLE      23
#define OV7690_CSI2_PHY_TCLK_TERM       0
#define OV7690_CSI2_PHY_TCLK_MISS       1
#define OV7690_CSI2_PHY_TCLK_SETTLE     14
With this clock polarity
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY; lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE; lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY; lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE; lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY; lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE; lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0; isp_csi2_complexio_lanes_config(&isp->isp_csi2, &lanecfg);
Michael

Michael Trimarchi

author

2010-01-12 17:32 UTC #7 lore raw

Hi all,

Quoted 14 lines · Sergio

Quoted 9 lines
-----Original Message-----
From: Michael Trimarchi [mailto:[email protected]]
Sent: Tuesday, January 12, 2010 7:15 AM
To: Aguirre, Sergio
Cc: Nishanth Menon; [email protected]; linux- [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Quoted 4 lines
Hi all,
Now I have a good camera pcb and I can test again the driver. My board is an overo gumstix board.

Quoted 9 lines

Excellent!
Please let me know if you're having issues with it.
Thanks for your interest!
Regards,
Sergio

maybe I have done some mistake during writing the email, but I have asked few things inside the email. The camera part is ok because I have written a driver using the ov538 bridge but I have some problem in configuring the isp omap3 device. It opens correctly the camera, and set xclk frequency. Then seems that vsync and hsync are not routed to the engine because I don't receive any interrupt.

Quoted 152 lines

Quoted 152 lines
Quoted 73 lines · Sergio Alberto
Hi Michael,
Quoted 30 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of michael
Sent: Sunday, October 04, 2009 7:29 PM
To: Nishanth Menon
Cc: [email protected]; [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Hi,
cc linux-media
Quoted 6 lines · Nishanth Menon
michael said the following on 10/03/2009 06:13 PM:
Quoted 4 lines
I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:
- datalane configuration
CSI2 Data lanes - each CSI2 lane is a differential pair.
And, at least 1
Quoted 1 line
clock and data lane is used in devices.
Sorry can you explain a little bit more. I have the camera connected to the
cam_hs and cam_vs and the data is 8Bit. I use the the isp init structure. The sccb bus works great and I can send configuration to it,
but I don't receive any interrupt from the ics, seems that it doen't see
the transaction:
Quoted 7 lines
The ISPCCDC: ###CCDC SYN_MODE=0x31704 seems ok.
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSFALL,
Can you try with ISPCTRL_SYNC_DETECT_VSRISE ?
Quoted 21 lines
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
and I don't know the meaning of
Quoted 11 lines
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY;
lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE;
lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY;
lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE;
lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY;
lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE;
lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0;
Quoted 5 lines
This is the physical connection details:
- The .pol field stands for the differntial pair polarity. (i.e. the order in which the negative and positive connections are pugged in to the CSI2 ComplexIO module)
What exact the meaning of the pol, sorry? I have a signal that is connected
to a pin. If the pos is avalaible can I use it?
It's not important how to route the signal but don't route on the same lane.
Is it right?
This is the timing of the camera so I can check signal, but I don't receive interrupt
of isp engine
The camera is direct connected to the
camera omap camera signal and using the oscilloscope I can see the hs/vs signal
The hs is low and go up, like the vs signal. I have only one camera with that use D0 to D7 data bit.
http://www.gumstix.net/Hardware/view/I/O-connectors-cabling/Gumstix-Overo-
27-pin-connector-J5-to-manage-camera-controls/112.html
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSRISE,
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
This is my initial configuration
#define OV7690_CSI2_CLOCK_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA0_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA1_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_CLOCK_LANE          1        /* Clock lane position: 1
*/
#define OV7690_CSI2_DATA0_LANE 2 /* Data0 lane position: 2
*/
#define OV7690_CSI2_DATA1_LANE 3 /* Data1 lane position: 3
*/
tim#define OV7690_CSI2_PHY_THS_TERM 2
#define OV7690_CSI2_PHY_THS_SETTLE      23
#define OV7690_CSI2_PHY_TCLK_TERM       0
#define OV7690_CSI2_PHY_TCLK_MISS       1
#define OV7690_CSI2_PHY_TCLK_SETTLE     14
With this clock polarity
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY; lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE; lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY; lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE; lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY; lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE; lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0; isp_csi2_complexio_lanes_config(&isp->isp_csi2, &lanecfg);

Quoted 2 lines

Quoted 1 line
Michael
--

Regards Michael

Quoted 4 lines

To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html

Michael Trimarchi

author

2010-01-12 21:28 UTC #8 lore raw

Hi,

Quoted 23 lines · Michael Trimarchi

Hi all,
Quoted 20 lines · Sergio
Quoted 9 lines
-----Original Message-----
From: Michael Trimarchi [mailto:[email protected]]
Sent: Tuesday, January 12, 2010 7:15 AM
To: Aguirre, Sergio
Cc: Nishanth Menon; [email protected]; linux- [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Quoted 4 lines
Hi all,
Now I have a good camera pcb and I can test again the driver. My board is an overo gumstix board.
Excellent!
Please let me know if you're having issues with it.
Thanks for your interest!

Quoted 8 lines

Quoted 3 lines
Regards,
Sergio
maybe I have done some mistake during writing the email, but I have asked few things inside the email. The camera part is ok because I have written a driver using the ov538 bridge but I have some problem in configuring the isp omap3 device. It opens correctly the camera, and set xclk frequency. Then seems that vsync and hsync are not routed to the engine because I don't receive any interrupt.

drivers/media/video/isp/isp.c +2 -0

@@ -299,6 +299,7 @@ static void isp_enable_interrupts(struct device *dev)
               | IRQ0ENABLE_CSIA_IRQ
               | IRQ0ENABLE_CSIB_IRQ | IRQ0ENABLE_HIST_DONE_IRQ
               | IRQ0ENABLE_H3A_AWB_DONE_IRQ | IRQ0ENABLE_H3A_AF_DONE_IRQ
+               | IRQ0ENABLE_HS_VS_IRQ
               | isp->interrupts;
 
       if (CCDC_PREV_CAPTURE(isp))

@@ -328,6 +329,7 @@ static void isp_disable_interrupts(struct device *dev)
               | IRQ0ENABLE_CSIA_IRQ
               | IRQ0ENABLE_CSIB_IRQ | IRQ0ENABLE_HIST_DONE_IRQ
               | IRQ0ENABLE_H3A_AWB_DONE_IRQ | IRQ0ENABLE_H3A_AF_DONE_IRQ
+               | IRQ0ENABLE_HS_VS_IRQ
               | isp->interrupts);

Adding this in the irq mask give me interrupt from the camera, but I don't undestarstand why they are disabled. Are they disabled in the latest git code?

how can I get the vrise?

.hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSFALL,

Michael

Quoted 168 lines

Quoted 153 lines
Quoted 153 lines
Quoted 73 lines · Sergio Alberto
Hi Michael,
Quoted 30 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of michael
Sent: Sunday, October 04, 2009 7:29 PM
To: Nishanth Menon
Cc: [email protected]; [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Hi,
cc linux-media
Quoted 6 lines · Nishanth Menon
michael said the following on 10/03/2009 06:13 PM:
Quoted 4 lines
I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:
- datalane configuration
CSI2 Data lanes - each CSI2 lane is a differential pair.
And, at least 1
Quoted 1 line
clock and data lane is used in devices.
Sorry can you explain a little bit more. I have the camera connected to the
cam_hs and cam_vs and the data is 8Bit. I use the the isp init structure. The sccb bus works great and I can send configuration to it,
but I don't receive any interrupt from the ics, seems that it doen't see
the transaction:
Quoted 7 lines
The ISPCCDC: ###CCDC SYN_MODE=0x31704 seems ok.
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSFALL,
Can you try with ISPCTRL_SYNC_DETECT_VSRISE ?
Quoted 21 lines
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
and I don't know the meaning of
Quoted 11 lines
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY;
lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE;
lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY;
lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE;
lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY;
lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE;
lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0;
Quoted 5 lines
This is the physical connection details:
- The .pol field stands for the differntial pair polarity. (i.e. the order in which the negative and positive connections are pugged in to the CSI2 ComplexIO module)
What exact the meaning of the pol, sorry? I have a signal that is connected
to a pin. If the pos is avalaible can I use it?
It's not important how to route the signal but don't route on the same lane.
Is it right?
This is the timing of the camera so I can check signal, but I don't receive interrupt
of isp engine
The camera is direct connected to the
camera omap camera signal and using the oscilloscope I can see the hs/vs signal
The hs is low and go up, like the vs signal. I have only one camera with that use D0 to D7 data bit.
http://www.gumstix.net/Hardware/view/I/O-connectors-cabling/Gumstix-Overo-
27-pin-connector-J5-to-manage-camera-controls/112.html
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSRISE,
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
This is my initial configuration
#define OV7690_CSI2_CLOCK_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA0_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA1_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_CLOCK_LANE          1        /* Clock lane position: 1
*/
#define OV7690_CSI2_DATA0_LANE 2 /* Data0 lane position: 2
*/
#define OV7690_CSI2_DATA1_LANE 3 /* Data1 lane position: 3
*/
tim#define OV7690_CSI2_PHY_THS_TERM 2
#define OV7690_CSI2_PHY_THS_SETTLE      23
#define OV7690_CSI2_PHY_TCLK_TERM       0
#define OV7690_CSI2_PHY_TCLK_MISS       1
#define OV7690_CSI2_PHY_TCLK_SETTLE     14
With this clock polarity
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY; lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE; lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY; lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE; lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY; lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE; lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0; isp_csi2_complexio_lanes_config(&isp->isp_csi2, &lanecfg);
Quoted 2 lines
Quoted 1 line
Michael
Regards Michael
Quoted 4 lines
To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Signature · 3 lines
To unsubscribe from this list: send the line "unsubscribe linux-media" in
the body of a message to [email protected]
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Aguirre, Sergio

2010-01-12 22:09 UTC #9 lore raw

Michael,

Quoted 65 lines

-----Original Message-----
From: Michael Trimarchi [mailto:[email protected]]
Sent: Tuesday, January 12, 2010 3:28 PM
To: Aguirre, Sergio
Cc: Nishanth Menon; [email protected]; linux- [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Hi,
Quoted 36 lines · Michael Trimarchi
Hi all,
Quoted 15 lines · Sergio
Quoted 9 lines
-----Original Message-----
From: Michael Trimarchi [mailto:[email protected]]
Sent: Tuesday, January 12, 2010 7:15 AM
To: Aguirre, Sergio
Cc: Nishanth Menon; [email protected]; linux- [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Quoted 5 lines
Hi all,
Now I have a good camera pcb and I can test again the driver. My board is
an overo gumstix board.
Quoted 9 lines
Excellent!
Please let me know if you're having issues with it.
Thanks for your interest!
Regards,
Sergio
maybe I have done some mistake during writing the email, but I have asked few things inside the email.
The camera part is ok because I have written a driver using the ov538 bridge but I have some problem
in configuring the isp omap3 device. It opens correctly the camera, and set xclk frequency. Then
seems that vsync and hsync are not routed to the engine because I don't receive any interrupt.
drivers/media/video/isp/isp.c +2 -0
@@ -299,6 +299,7 @@ static void isp_enable_interrupts(struct device *dev)
                | IRQ0ENABLE_CSIA_IRQ
                | IRQ0ENABLE_CSIB_IRQ | IRQ0ENABLE_HIST_DONE_IRQ
                | IRQ0ENABLE_H3A_AWB_DONE_IRQ | IRQ0ENABLE_H3A_AF_DONE_IRQ
+               | IRQ0ENABLE_HS_VS_IRQ
                | isp->interrupts;
 
        if (CCDC_PREV_CAPTURE(isp))
@@ -328,6 +329,7 @@ static void isp_disable_interrupts(struct device *dev)
                | IRQ0ENABLE_CSIA_IRQ
                | IRQ0ENABLE_CSIB_IRQ | IRQ0ENABLE_HIST_DONE_IRQ
                | IRQ0ENABLE_H3A_AWB_DONE_IRQ | IRQ0ENABLE_H3A_AF_DONE_IRQ
+               | IRQ0ENABLE_HS_VS_IRQ
                | isp->interrupts);
 

Quoted 3 lines

Adding this in the irq mask give me interrupt from the camera, but I don't undestarstand
why they are disabled. Are they disabled in the latest git code?

In the past, we used to rely on HS_VS for signaling when to do some actions, like enable ISP preview sub-module, and also had VD0 and VD1 programmable interrupts to do other actions.

Nowadays, the usage has changed. We don't really use HS_VS anymore. And we rely mainly on VD0 (generated based on CCDC input) for doing many interframe operations (like targeting for next buffer in the queue, and updating some other settings.)

In conclusion, we disabled HS_VS, because we don't use it anymore.

Quoted 4 lines

how can I get the vrise?
.hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSFALL,

.hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSRISE,

I'm interested in seeing your board file in which you configure interface from sensor to ISP. (See arch/arm/mach-omap2/board-zoom-camera.c for how I use it)

Regards,
Sergio

Quoted 179 lines

Michael
Quoted 86 lines
Quoted 86 lines
Quoted 86 lines
Quoted 73 lines · Sergio Alberto
Hi Michael,
Quoted 30 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of michael
Sent: Sunday, October 04, 2009 7:29 PM
To: Nishanth Menon
Cc: [email protected]; [email protected]
Subject: Re: ISP OMAP3 camera support ov7690
Hi,
cc linux-media
Quoted 6 lines · Nishanth Menon
michael said the following on 10/03/2009 06:13 PM:
Quoted 4 lines
I'm writing a driver to support the ov7690 camera and I have some question about the meaning of:
- datalane configuration
CSI2 Data lanes - each CSI2 lane is a differential pair.
And, at least 1
Quoted 1 line
clock and data lane is used in devices.
Sorry can you explain a little bit more. I have the camera connected to the
cam_hs and cam_vs and the data is 8Bit. I use the the isp init structure. The sccb bus works great and I can send configuration to it,
but I don't receive any interrupt from the ics, seems that it doen't see
the transaction:
Quoted 7 lines
The ISPCCDC: ###CCDC SYN_MODE=0x31704 seems ok.
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSFALL,
Can you try with ISPCTRL_SYNC_DETECT_VSRISE ?
Quoted 21 lines
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
and I don't know the meaning of
Quoted 11 lines
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY;
lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE;
lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY;
lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE;
lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY;
lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE;
lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0;
Quoted 5 lines
This is the physical connection details:
- The .pol field stands for the differntial pair polarity. (i.e. the order in which the negative and positive connections are pugged in to the CSI2 ComplexIO module)
What exact the meaning of the pol, sorry? I have a signal that is connected
to a pin. If the pos is avalaible can I use it?
It's not important how to route the signal but don't route on the same lane.
Is it right?
Quoted 6 lines
Quoted 6 lines
Quoted 6 lines
This is the timing of the camera so I can check signal, but I don't receive interrupt
of isp engine
The camera is direct connected to the
camera omap camera signal and using the oscilloscope I can see the
hs/vs
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
signal
The hs is low and go up, like the vs signal. I have only one camera with that use D0 to D7 data bit.
http://www.gumstix.net/Hardware/view/I/O-connectors-cabling/Gumstix-
Overo-
Quoted 59 lines
Quoted 59 lines
Quoted 59 lines
27-pin-connector-J5-to-manage-camera-controls/112.html
static struct isp_interface_config ov7690_if_config = {
        .ccdc_par_ser           = ISP_CSIA,
        .dataline_shift         = 0x0,
        .hsvs_syncdetect        = ISPCTRL_SYNC_DETECT_VSRISE,
        .strobe                 = 0x0,
        .prestrobe              = 0x0,
        .shutter                = 0x0,
        .wenlog                 = ISPCCDC_CFG_WENLOG_AND,
        .wait_hs_vs             = 0x4,
        .raw_fmt_in             = ISPCCDC_INPUT_FMT_GR_BG,
        .u.csi.crc              = 0x0,
        .u.csi.mode             = 0x0,
        .u.csi.edge             = 0x0,
        .u.csi.signalling       = 0x0,
        .u.csi.strobe_clock_inv = 0x0,
        .u.csi.vs_edge          = 0x0,
        .u.csi.channel          = 0x0,
        .u.csi.vpclk            = 0x1,
        .u.csi.data_start       = 0x0,
        .u.csi.data_size        = 0x0,
        .u.csi.format           = V4L2_PIX_FMT_YUYV,
};
This is my initial configuration
#define OV7690_CSI2_CLOCK_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA0_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_DATA1_POLARITY      0       /* +/- pin order */
#define OV7690_CSI2_CLOCK_LANE          1        /* Clock lane
position: 1
*/
#define OV7690_CSI2_DATA0_LANE 2 /* Data0 lane
position: 2
*/
#define OV7690_CSI2_DATA1_LANE 3 /* Data1 lane
position: 3
*/
tim#define OV7690_CSI2_PHY_THS_TERM 2
#define OV7690_CSI2_PHY_THS_SETTLE      23
#define OV7690_CSI2_PHY_TCLK_TERM       0
#define OV7690_CSI2_PHY_TCLK_MISS       1
#define OV7690_CSI2_PHY_TCLK_SETTLE     14
With this clock polarity
lanecfg.clk.pol = OV7690_CSI2_CLOCK_POLARITY; lanecfg.clk.pos = OV7690_CSI2_CLOCK_LANE; lanecfg.data[0].pol = OV7690_CSI2_DATA0_POLARITY; lanecfg.data[0].pos = OV7690_CSI2_DATA0_LANE; lanecfg.data[1].pol = OV7690_CSI2_DATA1_POLARITY; lanecfg.data[1].pos = OV7690_CSI2_DATA1_LANE; lanecfg.data[2].pol = 0;
lanecfg.data[2].pos = 0;
lanecfg.data[3].pol = 0;
lanecfg.data[3].pos = 0; isp_csi2_complexio_lanes_config(&isp->isp_csi2, &lanecfg);
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Michael
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Regards Michael
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Michael Trimarchi

author

2010-01-13 10:18 UTC #10 lore raw

Hi,

I have done a step ahead maybe:

The camera has this output format:

YUYV     ---> the first use the CCDC_OTHERS_MEM, so seems that it needs the WEN signal to syncronize (I don't have this one)
RGB565   ---> is not supported
RAW8     ---> is supported by the ISP but seems that is not implemented as a isp formats

So I can't use the first one but I can use the last one because the pipeline support RAW format, the data path is the same of RAW10 expet for the autofocus module. If all is correct what are the steps?

- add the isp_format
- add in the if confidition this data format and use the same path of RAW10
...

Regards

Michael