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KMV: VMX: consult IA32_VMX_EPT_VPID_CAP to determine EPT paging-structure memory type

PATCH In review Gui Jianfeng 3 participants 4 messages Mar 22, 2010 – Mar 26, 2010

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Gui Jianfeng

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#0 lore raw

PATCH 1/1 KMV: VMX: consult IA32_VMX_EPT_VPID_CAP to determine EPT paging-structure memory type

According to SDM, we need to configure EPT paging-structure memory type by consulting IA32_VMX_EPT_VPID_CAP.

Signed-off-by Gui Jianfeng <[email protected]>
---
 arch/x86/include/asm/vmx.h |    2 ++
 arch/x86/kvm/vmx.c         |   12 +++++++++---
 2 files changed, 11 insertions(+), 3 deletions(-)
arch/x86/include/asm/vmx.h +2 -0
index fb9a080..1b33a60 100644
@@ -374,6 +374,8 @@ enum vmcs_field {
 #define VMX_EPT_MT_EPTE_SHIFT			3
 #define VMX_EPT_GAW_EPTP_SHIFT			3
 #define VMX_EPT_DEFAULT_MT			0x6ull
+#define VMX_EPT_MT_WRBACK			0x6ull
+#define VMX_EPT_MT_UNCACHABLE			0x0ull
 #define VMX_EPT_READABLE_MASK			0x1ull
 #define VMX_EPT_WRITABLE_MASK			0x2ull
 #define VMX_EPT_EXECUTABLE_MASK			0x4ull
arch/x86/kvm/vmx.c +9 -3
index 06108f3..f971b9b 100644
@@ -1804,9 +1804,15 @@ static u64 construct_eptp(unsigned long root_hpa)
 {
 	u64 eptp;
 
-	/* TODO write the value reading from MSR */
-	eptp = VMX_EPT_DEFAULT_MT |
-		VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
+	if (cpu_has_vmx_eptp_writeback())
+		eptp = VMX_EPT_MT_WRBACK |
+			VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
+	else if (cpu_has_vmx_eptp_uncacheable())
+		eptp = VMX_EPT_MT_UNCACHABLE |
+			VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
+	else
+		BUG();
+
 	eptp |= (root_hpa & PAGE_MASK);
 
 	return eptp;
Signature · 1 line
1.6.5.2
#1 lore raw
Quoted 27 lines · On Monday 22 March 2010 17:06:42 Gui Jianfeng wrote:

According to SDM, we need to configure EPT paging-structure memory type by consulting IA32_VMX_EPT_VPID_CAP.

Signed-off-by Gui Jianfeng <[email protected]>
---
 arch/x86/include/asm/vmx.h |    2 ++
 arch/x86/kvm/vmx.c         |   12 +++++++++---
 2 files changed, 11 insertions(+), 3 deletions(-)
arch/x86/include/asm/vmx.h +2 -0
index fb9a080..1b33a60 100644
@@ -374,6 +374,8 @@ enum vmcs_field {
 #define VMX_EPT_MT_EPTE_SHIFT			3
 #define VMX_EPT_GAW_EPTP_SHIFT			3
 #define VMX_EPT_DEFAULT_MT			0x6ull
+#define VMX_EPT_MT_WRBACK			0x6ull
+#define VMX_EPT_MT_UNCACHABLE			0x0ull
 #define VMX_EPT_READABLE_MASK			0x1ull
 #define VMX_EPT_WRITABLE_MASK			0x2ull
 #define VMX_EPT_EXECUTABLE_MASK			0x4ull
arch/x86/kvm/vmx.c +0 -0
index 06108f3..f971b9b 100644

arch/x86/kvm/vmx.c static u64 construct_eptp(unsigned long root_hpa) · line 1809

Quoted 9 lines
arch/x86/kvm/vmx.c +3 -3
@@ -1804,9 +1804,15 @@ static u64 construct_eptp(unsigned long root_hpa)
 {
 	u64 eptp;
 
-	/* TODO write the value reading from MSR */
-	eptp = VMX_EPT_DEFAULT_MT |
-		VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
+	if (cpu_has_vmx_eptp_writeback())
+		eptp = VMX_EPT_MT_WRBACK |
+			VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;

I prefer to ensure WB is supported and used as default. Otherwise it would be a big trouble for memory subsystem(to use UC for all memory). Both WB and UC EPT memory types are ensured to be support in hardware.

And you can remove VMX_EPT_DEFAULT_MT as well.

Signature · 2 lines
regards
Yang, Sheng
Quoted 10 lines
arch/x86/kvm/vmx.c +6 -0
+	else if (cpu_has_vmx_eptp_uncacheable())
+		eptp = VMX_EPT_MT_UNCACHABLE |
+			VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
+	else
+		BUG();
+
 	eptp |= (root_hpa & PAGE_MASK);
 
 	return eptp;
#2 lore raw
Quoted 20 lines · Sheng Yang
Quoted 6 lines
arch/x86/kvm/vmx.c +0 -0
index 06108f3..f971b9b 100644

arch/x86/kvm/vmx.c static u64 construct_eptp(unsigned long root_hpa) · line 1810

Quoted 10 lines
arch/x86/kvm/vmx.c +3 -3
@@ -1804,9 +1804,15 @@ static u64 construct_eptp(unsigned long root_hpa)
  {
  	u64 eptp;
 
-	/* TODO write the value reading from MSR */
-	eptp = VMX_EPT_DEFAULT_MT |
-		VMX_EPT_DEFAULT_GAW<<  VMX_EPT_GAW_EPTP_SHIFT;
+	if (cpu_has_vmx_eptp_writeback())
+		eptp = VMX_EPT_MT_WRBACK |
+			VMX_EPT_DEFAULT_GAW<<  VMX_EPT_GAW_EPTP_SHIFT;

I prefer to ensure WB is supported and used as default. Otherwise it would be a big trouble for memory subsystem(to use UC for all memory). Both WB and UC EPT memory types are ensured to be support in hardware.

Quoted 2 lines

And you can remove VMX_EPT_DEFAULT_MT as well.

I agree, hopefully we never ever see a cpu that doesn't support EPT WB.

Signature · 1 line
error compiling committee.c: too many arguments to function
author
#3 lore raw
Quoted 23 lines · Avi Kivity
Quoted 22 lines · Sheng Yang
Quoted 6 lines
arch/x86/kvm/vmx.c +0 -0
index 06108f3..f971b9b 100644

arch/x86/kvm/vmx.c static u64 construct_eptp(unsigned long root_hpa) · line 1810

Quoted 10 lines
arch/x86/kvm/vmx.c +3 -3
@@ -1804,9 +1804,15 @@ static u64 construct_eptp(unsigned long root_hpa)
  {
      u64 eptp;
 
-    /* TODO write the value reading from MSR */
-    eptp = VMX_EPT_DEFAULT_MT |
-        VMX_EPT_DEFAULT_GAW<<  VMX_EPT_GAW_EPTP_SHIFT;
+    if (cpu_has_vmx_eptp_writeback())
+        eptp = VMX_EPT_MT_WRBACK |
+            VMX_EPT_DEFAULT_GAW<<  VMX_EPT_GAW_EPTP_SHIFT;

I prefer to ensure WB is supported and used as default. Otherwise it would be
a big trouble for memory subsystem(to use UC for all memory). Both WB and UC
EPT memory types are ensured to be support in hardware.

Quoted 4 lines
Quoted 2 lines

And you can remove VMX_EPT_DEFAULT_MT as well.

I agree, hopefully we never ever see a cpu that doesn't support EPT WB.

OK, seems we don't need to have this concern. :)

Quoted 1 line