MIPS Magnum conversion to qdev

index b8e6fee..b75e1e6 100644
@@ -586,6 +586,7 @@ enum {
 
 int cpu_mips_exec(CPUMIPSState *s);
 CPUMIPSState *cpu_mips_init(const char *cpu_model);
+int cpu_mips_init_inplace(CPUMIPSState *env, const char *cpu_model);
 //~ uint32_t cpu_mips_get_clock (void);
 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 

index 20b66a8..558f6ac 100644
@@ -12580,15 +12580,13 @@ static void mips_tcg_init(void)
 
 #include "translate_init.c"
 
-CPUMIPSState *cpu_mips_init (const char *cpu_model)
+int cpu_mips_init_inplace(CPUMIPSState *env, const char *cpu_model)
 {
-    CPUMIPSState *env;
     const mips_def_t *def;
 
     def = cpu_mips_find_by_name(cpu_model);
     if (!def)
-        return NULL;
-    env = qemu_mallocz(sizeof(CPUMIPSState));
+        return -1;
     env->cpu_model = def;
     env->cpu_model_str = cpu_model;
 

@@ -12601,6 +12599,16 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model)
     mips_tcg_init();
     cpu_reset(env);
     qemu_init_vcpu(env);
+    return 0;
+}
+
+CPUMIPSState *cpu_mips_init (const char *cpu_model)
+{
+    CPUMIPSState *env;
+
+    env = qemu_mallocz(sizeof(CPUMIPSState));
+    if (!cpu_mips_init_inplace(env, cpu_model))
+        return NULL;
     return env;
 }
 

index db82b41..495b3fd 100644
@@ -1,5 +1,7 @@
 #ifndef HW_MIPS_CPUDEVS_H
 #define HW_MIPS_CPUDEVS_H
+#include "qdev.h"
+
 /* Definitions for MIPS CPU internal devices.  */
 
 /* mips_addr.c */

@@ -8,6 +10,8 @@ uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
 
 /* mips_int.c */
 void cpu_mips_irq_init_cpu(CPUState *env);
+BusState *cpu_mips_init_cpu(const char *model);
+void cpu_mips_register(DeviceInfo *info);
 
 /* mips_timer.c */
 void cpu_mips_clock_init(CPUState *);

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index 71b05a2..78ef8f0 100644
@@ -43,12 +43,6 @@ enum jazz_model_e
     JAZZ_PICA61,
 };
 
-static void main_cpu_reset(void *opaque)
-{
-    CPUState *env = opaque;
-    cpu_reset(env);
-}
-
 static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
 {
     return cpu_inw(0x71);

@@ -128,7 +122,7 @@ void mips_jazz_init (ram_addr_t ram_size,
 {
     char *filename;
     int bios_size, n;
-    CPUState *env;
+    BusState *cpu;
     qemu_irq *rc4030, *i8259;
     rc4030_dma *dmas;
     void* rc4030_opaque;

@@ -150,12 +144,11 @@ void mips_jazz_init (ram_addr_t ram_size,
         cpu_model = "24Kf";
 #endif
     }
-    env = cpu_init(cpu_model);
-    if (!env) {
+    cpu = cpu_mips_init_cpu(cpu_model);
+    if (!cpu) {
         fprintf(stderr, "Unable to find CPU definition\n");
         exit(1);
     }
-    qemu_register_reset(main_cpu_reset, env);
 
     /* allocate RAM */
     ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size);

@@ -184,17 +177,13 @@ void mips_jazz_init (ram_addr_t ram_size,
         exit(1);
     }
 
-    /* Init CPU internal devices */
-    cpu_mips_irq_init_cpu(env);
-    cpu_mips_clock_init(env);
-
     /* Chipset */
-    rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
+    rc4030_opaque = rc4030_init(qdev_get_gpio_in(cpu->parent, 6), qdev_get_gpio_in(cpu->parent, 3), &rc4030, &dmas);
     s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 
     /* ISA devices */
-    i8259 = i8259_init(env->irq[4]);
+    i8259 = i8259_init(qdev_get_gpio_in(cpu->parent, 4));
     isa_bus_new(NULL);
     isa_bus_irqs(i8259);
     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);

index 617ea10..55fb701 100644
@@ -23,15 +23,6 @@ void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
 /* jazz_led.c */
 extern void jazz_led_init(target_phys_addr_t base);
 
-/* rc4030.c */
-typedef struct rc4030DMAState *rc4030_dma;
-void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
-void rc4030_dma_read(void *dma, uint8_t *buf, int len);
-void rc4030_dma_write(void *dma, uint8_t *buf, int len);
-
-void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
-                  qemu_irq **irqs, rc4030_dma **dmas);
-
 /* dp8393x.c */
 void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
                   qemu_irq irq, void* mem_opaque,

index 78ef8f0..c000fd3 100644
@@ -36,6 +36,7 @@
 #include "mips-bios.h"
 #include "loader.h"
 #include "mc146818rtc.h"
+#include "rc4030.h"
 
 enum jazz_model_e
 {

@@ -178,7 +179,7 @@ void mips_jazz_init (ram_addr_t ram_size,
     }
 
     /* Chipset */
-    rc4030_opaque = rc4030_init(qdev_get_gpio_in(cpu->parent, 6), qdev_get_gpio_in(cpu->parent, 3), &rc4030, &dmas);
+    rc4030_opaque = rc4030_init(cpu, &rc4030, &dmas);
     s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 

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index 47bb4b2..67b8d83 100644
@@ -40,6 +40,7 @@
 #include "net.h"
 #include "gdbstub.h"
 #include "hw/smbios.h"
+#include "hw/rc4030.h"
 
 #ifdef TARGET_SPARC
 int graphic_width = 1024;

@@ -640,3 +641,23 @@ int xen_available(void)
     return 0;
 #endif
 }
+
+#ifndef TARGET_MIPS
+void rc4030_init_irq(RC4030Device *dev, qemu_irq *p, int rc4030irq)
+{
+}
+
+void rc4030_qdev_register(RC4030DeviceInfo *info)
+{
+}
+
+RC4030Device *rc4030_create(const char *name)
+{
+    return NULL;
+}
+
+RC4030Device *rc4030_create_simple(const char *name)
+{
+    return NULL;
+}
+#endif

index c000fd3..9663a3c 100644
@@ -252,7 +252,7 @@ void mips_jazz_init (ram_addr_t ram_size,
     cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
 
     /* Keyboard (i8042) */
-    i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
+    rc4030_create_simple("rc4030-i8042");
 
     /* Serial ports */
     if (serial_hds[0]) {

index 63b0249..e078fd9 100644
@@ -74,9 +74,6 @@ void *vmmouse_init(void *m);
 /* pckbd.c */
 
 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
-void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
-                   target_phys_addr_t base, ram_addr_t size,
-                   target_phys_addr_t mask);
 void i8042_isa_mouse_fake_event(void *opaque);
 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
 

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index 9663a3c..a027559 100644
@@ -271,8 +271,9 @@ void mips_jazz_init (ram_addr_t ram_size,
     }
 
     /* Parallel port */
-    if (parallel_hds[0])
-        parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
+    if (parallel_hds[0]) {
+        parallel_rc4030_init(parallel_hds[0]);
+    }
 
     /* Sound card */
     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */

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index e078fd9..61b5fbb 100644
@@ -23,7 +23,7 @@ void serial_set_frequency(SerialState *s, uint32_t frequency);
 
 typedef struct ParallelState ParallelState;
 ParallelState *parallel_init(int index, CharDriverState *chr);
-ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
+ParallelState *parallel_rc4030_init(CharDriverState *chr);
 
 /* i8259.c */
 

index a027559..1298bc1 100644
@@ -256,18 +256,10 @@ void mips_jazz_init (ram_addr_t ram_size,
 
     /* Serial ports */
     if (serial_hds[0]) {
-#ifdef TARGET_WORDS_BIGENDIAN
-        serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1);
-#else
-        serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
-#endif
+        serial_rc4030_init(0, serial_hds[0]);
     }
     if (serial_hds[1]) {
-#ifdef TARGET_WORDS_BIGENDIAN
-        serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1);
-#else
-        serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
-#endif
+        serial_rc4030_init(1, serial_hds[1]);
     }
 
     /* Parallel port */

index 61b5fbb..f5a479a 100644
@@ -17,6 +17,7 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                              CharDriverState *chr, int ioregister,
                              int be);
 SerialState *serial_isa_init(int index, CharDriverState *chr);
+SerialState *serial_rc4030_init(int index, CharDriverState *chr);
 void serial_set_frequency(SerialState *s, uint32_t frequency);
 
 /* parallel.c */

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index 55fb701..023d85c 100644
@@ -20,9 +20,6 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
 /* mipsnet.c */
 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
 
-/* jazz_led.c */
-extern void jazz_led_init(target_phys_addr_t base);
-
 /* dp8393x.c */
 void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
                   qemu_irq irq, void* mem_opaque,

index 1298bc1..8c3c956 100644
@@ -124,6 +124,7 @@ void mips_jazz_init (ram_addr_t ram_size,
     char *filename;
     int bios_size, n;
     BusState *cpu;
+    DeviceState *dev;
     qemu_irq *rc4030, *i8259;
     rc4030_dma *dmas;
     void* rc4030_opaque;

@@ -275,7 +276,8 @@ void mips_jazz_init (ram_addr_t ram_size,
     ds1225y_init(0x80009000, "nvram");
 
     /* LED indicator */
-    jazz_led_init(0x8000f000);
+    dev = qdev_create(NULL, "jazz-led");
+    qdev_init_nofail(dev);
 }
 
 static

index 8c3c956..b737cf3 100644
@@ -202,16 +202,18 @@ void mips_jazz_init (ram_addr_t ram_size,
 
     isa_mem_base = 0x11000000;
 
-    /* Video card */
-    switch (jazz_model) {
-    case JAZZ_MAGNUM:
-        g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
-        break;
-    case JAZZ_PICA61:
-        isa_vga_mm_init(0x40000000, 0x60000000, 0);
-        break;
-    default:
-        break;
+    /* Optional video card */
+    if (vga_interface_type != VGA_NONE) {
+        switch (jazz_model) {
+        case JAZZ_MAGNUM:
+            g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
+            break;
+        case JAZZ_PICA61:
+            isa_vga_mm_init(0x40000000, 0x60000000, 0);
+            break;
+        default:
+            break;
+        }
     }
 
     /* Network controller */

index b737cf3..96946e8 100644
@@ -209,7 +209,7 @@ void mips_jazz_init (ram_addr_t ram_size,
             g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
             break;
         case JAZZ_PICA61:
-            isa_vga_mm_init(0x40000000, 0x60000000, 0);
+            isa_create_simple("isa-vga-mm");
             break;
         default:
             break;

index f5a479a..acfed83 100644
@@ -154,8 +154,6 @@ extern enum vga_retrace_method vga_retrace_method;
 int isa_vga_init(void);
 int pci_vga_init(PCIBus *bus,
                  unsigned long vga_bios_offset, int vga_bios_size);
-int isa_vga_mm_init(target_phys_addr_t vram_base,
-                    target_phys_addr_t ctrl_base, int it_shift);
 
 /* cirrus_vga.c */
 void pci_cirrus_vga_init(PCIBus *bus);

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index b3e3676..9815f8d 100644
@@ -265,6 +265,7 @@ static struct {
     { .driver = "VGA",                  .flag = &default_vga       },
     { .driver = "cirrus-vga",           .flag = &default_vga       },
     { .driver = "vmware-svga",          .flag = &default_vga       },
+    { .driver = "isa-vga-mm",           .flag = &default_vga       },
 };
 
 static int default_driver_check(QemuOpts *opts, void *opaque)

index 3c8fb98..4b5e6ef 100644
@@ -21,6 +21,8 @@
 #include "mips.h"
 #include "console.h"
 #include "pixel_ops.h"
+#include "rc4030.h"
+#include "qdev-addr.h"
 
 //#define DEBUG_G364
 

@@ -37,7 +39,7 @@ typedef struct G364State {
     /* hardware */
     uint8_t *vram;
     ram_addr_t vram_offset;
-    int vram_size;
+    uint32_t vram_size;
     qemu_irq irq;
     /* registers */
     uint8_t color_palette[256][3];

@@ -53,6 +55,14 @@ typedef struct G364State {
     int blanked;
 } G364State;
 
+typedef struct RC4030G364State {
+    RC4030Device dev;
+    target_phys_addr_t iobase;
+    target_phys_addr_t vram;
+    uint32_t irq;
+    G364State state;
+} RC4030G364State;
+
 #define REG_ID       0x000000
 #define REG_BOOT     0x080000
 #define REG_DISPLAY  0x080118

@@ -279,9 +289,8 @@ static inline void g364fb_invalidate_display(void *opaque)
     }
 }
 
-static void g364fb_reset(void *opaque)
+static void g364fb_reset(G364State *s)
 {
-    G364State *s = opaque;
     qemu_irq_lower(s->irq);
 
     memset(s->color_palette, 0, sizeof(s->color_palette));

@@ -292,7 +301,13 @@ static void g364fb_reset(void *opaque)
     s->top_of_screen = 0;
     s->width = s->height = 0;
     memset(s->vram, 0, s->vram_size);
-    g364fb_invalidate_display(opaque);
+    g364fb_invalidate_display(s);
+}
+
+static void g364fb_reset1(DeviceState *d)
+{
+    G364State *s = &container_of(d, RC4030G364State, dev.qdev)->state;
+    g364fb_reset(s);
 }
 
 static void g364fb_screen_dump(void *opaque, const char *filename)

@@ -583,32 +598,47 @@ static void g364fb_save(QEMUFile *f, void *opaque)
     qemu_put_be32(f, s->height);
 }
 
-int g364fb_mm_init(target_phys_addr_t vram_base,
-                   target_phys_addr_t ctrl_base, int it_shift,
-                   qemu_irq irq)
+static int g364fb_init(RC4030Device *dev)
 {
-    G364State *s;
+    RC4030G364State *rc4030 = container_of(dev, RC4030G364State, dev);
+    G364State *s = &rc4030->state;
     int io_ctrl;
 
-    s = qemu_mallocz(sizeof(G364State));
-
-    s->vram_size = 8 * 1024 * 1024;
     s->vram_offset = qemu_ram_alloc(NULL, "g364fb.vram", s->vram_size);
     s->vram = qemu_get_ram_ptr(s->vram_offset);
-    s->irq = irq;
+    rc4030_init_irq(dev, &s->irq, rc4030->irq);
 
-    qemu_register_reset(g364fb_reset, s);
     register_savevm(NULL, "g364fb", 0, 1, g364fb_save, g364fb_load, s);
-    g364fb_reset(s);
 
     s->ds = graphic_console_init(g364fb_update_display,
                                  g364fb_invalidate_display,
                                  g364fb_screen_dump, NULL, s);
 
-    cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
+    cpu_register_physical_memory(rc4030->vram, s->vram_size, s->vram_offset);
 
     io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s);
-    cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
+    cpu_register_physical_memory(rc4030->iobase, 0x200000, io_ctrl);
 
     return 0;
 }
+
+static RC4030DeviceInfo g364fb_device_info = {
+    .qdev.name  = "rc4030-g364fb",
+    .qdev.size  = sizeof(RC4030G364State),
+    .qdev.reset = g364fb_reset1,
+    .init       = g364fb_init,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_TADDR("iobase", RC4030G364State, iobase, 0x60000000),
+        DEFINE_PROP_TADDR("vram", RC4030G364State, vram, 0x40000000),
+        DEFINE_PROP_HEX32("vram_size", RC4030G364State, state.vram_size, 8 * 1024 * 1024),
+        DEFINE_PROP_UINT32("irq", RC4030G364State, irq, 3),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
+static void g364fb_register_devices(void)
+{
+    rc4030_qdev_register(&g364fb_device_info);
+}
+
+device_init(g364fb_register_devices)

index 023d85c..aa790d8 100644
@@ -12,11 +12,6 @@ PCIBus *bonito_init(qemu_irq *pic);
 void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
 void ds1225y_set_protection(void *opaque, int protection);
 
-/* g364fb.c */
-int g364fb_mm_init(target_phys_addr_t vram_base,
-                   target_phys_addr_t ctrl_base, int it_shift,
-                   qemu_irq irq);
-
 /* mipsnet.c */
 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
 

index 96946e8..c4f3721 100644
@@ -206,7 +206,7 @@ void mips_jazz_init (ram_addr_t ram_size,
     if (vga_interface_type != VGA_NONE) {
         switch (jazz_model) {
         case JAZZ_MAGNUM:
-            g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
+            rc4030_create_simple("rc4030-g364fb");
             break;
         case JAZZ_PICA61:
             isa_create_simple("isa-vga-mm");

index 9815f8d..eb4c212 100644
@@ -266,6 +266,7 @@ static struct {
     { .driver = "cirrus-vga",           .flag = &default_vga       },
     { .driver = "vmware-svga",          .flag = &default_vga       },
     { .driver = "isa-vga-mm",           .flag = &default_vga       },
+    { .driver = "rc4030-g364fb",        .flag = &default_vga       },
 };
 
 static int default_driver_check(QemuOpts *opts, void *opaque)

index 2b91fa8..674d24f 100644
@@ -28,6 +28,8 @@
 #include "apic.h"
 #include "isa.h"
 #include "mc146818rtc.h"
+#include "sysbus.h"
+#include "qdev-addr.h"
 
 //#define DEBUG_CMOS
 //#define DEBUG_COALESCED

@@ -631,7 +633,6 @@ ISADevice *rtc_init(int base_year, qemu_irq intercept_irq)
 static ISADeviceInfo mc146818rtc_info = {
     .qdev.name     = "mc146818rtc",
     .qdev.size     = sizeof(RTCState),
-    .qdev.no_user  = 1,
     .qdev.vmsd     = &vmstate_rtc,
     .init          = rtc_initfn,
     .qdev.props    = (Property[]) {

@@ -640,8 +641,59 @@ static ISADeviceInfo mc146818rtc_info = {
     }
 };
 
+static uint32_t rtc_forward_readb(void *opaque, target_phys_addr_t addr)
+{
+    return cpu_inw(0x71);
+}
+
+static void rtc_forward_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+    cpu_outw(0x71, val & 0xff);
+}
+
+static CPUReadMemoryFunc * const rtc_forward_read[3] = {
+    rtc_forward_readb,
+    rtc_forward_readb,
+    rtc_forward_readb,
+};
+
+static CPUWriteMemoryFunc * const rtc_forward_write[3] = {
+    rtc_forward_writeb,
+    rtc_forward_writeb,
+    rtc_forward_writeb,
+};
+
+typedef struct RtcForwardState {
+    SysBusDevice busdev;
+    target_phys_addr_t iobase;
+    uint32_t size;
+} RtcForwardState;
+
+static int rtc_forward_init(SysBusDevice *dev)
+{
+    RtcForwardState *s = FROM_SYSBUS(RtcForwardState, dev);
+    int io;
+
+    io = cpu_register_io_memory(rtc_forward_read, rtc_forward_write, s);
+    cpu_register_physical_memory(s->iobase, s->size, io);
+
+    return 0;
+}
+
+static SysBusDeviceInfo rtc_forward_info = {
+    .qdev.name  = "rtc-forward",
+    .qdev.size  = sizeof(RtcForwardState),
+    .init       = rtc_forward_init,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_TADDR("iobase", RtcForwardState, iobase, 0x80004000),
+        DEFINE_PROP_HEX32("size", RtcForwardState, size, 0x1000),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
 static void mc146818rtc_register(void)
 {
     isa_qdev_register(&mc146818rtc_info);
+    sysbus_register_withprop(&rtc_forward_info);
 }
 device_init(mc146818rtc_register)

index c4f3721..b9c6b62 100644
@@ -44,28 +44,6 @@ enum jazz_model_e
     JAZZ_PICA61,
 };
 
-static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
-{
-    return cpu_inw(0x71);
-}
-
-static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    cpu_outw(0x71, val & 0xff);
-}
-
-static CPUReadMemoryFunc * const rtc_read[3] = {
-    rtc_readb,
-    rtc_readb,
-    rtc_readb,
-};
-
-static CPUWriteMemoryFunc * const rtc_write[3] = {
-    rtc_writeb,
-    rtc_writeb,
-    rtc_writeb,
-};
-
 static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     /* Nothing to do. That is only to ensure that

@@ -128,7 +106,7 @@ void mips_jazz_init (ram_addr_t ram_size,
     qemu_irq *rc4030, *i8259;
     rc4030_dma *dmas;
     void* rc4030_opaque;
-    int s_rtc, s_dma_dummy;
+    int s_dma_dummy;
     NICInfo *nd;
     PITState *pit;
     DriveInfo *fds[MAX_FD];

@@ -251,8 +229,8 @@ void mips_jazz_init (ram_addr_t ram_size,
 
     /* Real time clock */
     rtc_init(1980, NULL);
-    s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL);
-    cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
+    dev = qdev_create(NULL, "rtc-forward");
+    qdev_init_nofail(dev);
 
     /* Keyboard (i8042) */
     rc4030_create_simple("rc4030-i8042");

index 4e306de..c245151 100644
@@ -21,6 +21,7 @@
 #include "monitor.h"
 #include "sysbus.h"
 #include "isa.h"
+#include "qdev-addr.h"
 
 struct ISABus {
     BusState qbus;

@@ -53,6 +54,22 @@ ISABus *isa_bus_new(DeviceState *dev)
     return isabus;
 }
 
+typedef struct IsaBusState {
+    SysBusDevice dev;
+    target_phys_addr_t iobase;
+    uint32_t size;
+} IsaBusState;
+
+static int isabus_init(SysBusDevice *dev)
+{
+    IsaBusState *bus = DO_UPCAST(IsaBusState, dev, dev);
+
+    if (isa_bus_new(NULL) == NULL)
+        return -1;
+    isa_mmio_init(bus->iobase, bus->size, 0);
+    return 0;
+}
+
 void isa_bus_irqs(qemu_irq *irqs)
 {
     isabus->irqs = irqs;

@@ -157,9 +174,21 @@ static SysBusDeviceInfo isabus_bridge_info = {
     .qdev.no_user = 1,
 };
 
+static SysBusDeviceInfo isabus_info = {
+    .init = isabus_init,
+    .qdev.name  = "isabus",
+    .qdev.size  = sizeof(IsaBusState),
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_TADDR("iobase", IsaBusState, iobase, 0x90000000),
+        DEFINE_PROP_HEX32("size", IsaBusState, size, 0x1000000),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
 static void isabus_register_devices(void)
 {
     sysbus_register_withprop(&isabus_bridge_info);
+    sysbus_register_withprop(&isabus_info);
 }
 
 device_init(isabus_register_devices)

index b9c6b62..cf0001e 100644
@@ -163,23 +163,15 @@ void mips_jazz_init (ram_addr_t ram_size,
     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 
     /* ISA devices */
+    dev = qdev_create(NULL, "isabus");
+    qdev_init_nofail(dev);
     i8259 = i8259_init(qdev_get_gpio_in(cpu->parent, 4));
-    isa_bus_new(NULL);
     isa_bus_irqs(i8259);
     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
     DMA_init(0, cpu_exit_irq);
     pit = pit_init(0x40, i8259[0]);
     pcspk_init(pit);
 
-    /* ISA IO space at 0x90000000 */
-#ifdef TARGET_WORDS_BIGENDIAN
-    isa_mmio_init(0x90000000, 0x01000000, 1);
-#else
-    isa_mmio_init(0x90000000, 0x01000000, 0);
-#endif
-
-    isa_mem_base = 0x11000000;
-
     /* Optional video card */
     if (vga_interface_type != VGA_NONE) {
         switch (jazz_model) {

index e65e4d1..f8fd9f5 100644
@@ -21,6 +21,8 @@
 #include "qemu-timer.h"
 #include "net.h"
 #include "mips.h"
+#include "rc4030.h"
+#include "qdev-addr.h"
 
 //#define DEBUG_SONIC
 

@@ -147,7 +149,7 @@ do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
 
 typedef struct dp8393xState {
     /* Hardware */
-    int it_shift;
+    uint32_t it_shift;
     qemu_irq irq;
 #ifdef DEBUG_SONIC
     int irq_level;

@@ -869,8 +871,6 @@ static void nic_cleanup(VLANClientState *nc)
 
     qemu_del_timer(s->watchdog);
     qemu_free_timer(s->watchdog);
-
-    qemu_free(s);
 }
 
 static NetClientInfo net_dp83932_info = {

@@ -881,33 +881,53 @@ static NetClientInfo net_dp83932_info = {
     .cleanup = nic_cleanup,
 };
 
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
-                  qemu_irq irq, void* mem_opaque,
-                  void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
-{
-    dp8393xState *s;
-
-    qemu_check_nic_model(nd, "dp83932");
+typedef struct RC4030dp83932State {
+    RC4030Device dev;
+    target_phys_addr_t iobase;
+    uint32_t irq;
+    dp8393xState state;
+} RC4030dp83932State;
 
-    s = qemu_mallocz(sizeof(dp8393xState));
+static int dp83932_rc4030_init(RC4030Device *dev)
+{
+    RC4030dp83932State *rc4030 = DO_UPCAST(RC4030dp83932State, dev, dev);
+    dp8393xState *s = &rc4030->state;
 
-    s->mem_opaque = mem_opaque;
-    s->memory_rw = memory_rw;
-    s->it_shift = it_shift;
-    s->irq = irq;
+    s->mem_opaque = rc4030_get_opaque();
+    s->memory_rw = rc4030_dma_memory_rw;
+    rc4030_init_irq(dev, &s->irq, rc4030->irq);
     s->watchdog = qemu_new_timer(vm_clock, dp8393x_watchdog, s);
     s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
 
-    memcpy(s->conf.macaddr.a, nd->macaddr, sizeof(s->conf.macaddr));
-    s->conf.vlan = nd->vlan;
-    s->conf.peer = nd->netdev;
-
-    s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s);
-
+    qemu_macaddr_default_if_unset(&s->conf.macaddr);
+    s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, dev->qdev.info->name, dev->qdev.id, s);
     qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
+
     qemu_register_reset(nic_reset, s);
     nic_reset(s);
 
     s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
-    cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
+    cpu_register_physical_memory(rc4030->iobase, 0x40 << s->it_shift, s->mmio_index);
+
+    return 0;
 }
+
+static RC4030DeviceInfo dp83932_rc4030_info = {
+    .qdev.name  = "rc4030-dp83932",
+    .qdev.size  = sizeof(RC4030dp83932State),
+    .init       = dp83932_rc4030_init,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_TADDR("iobase",   RC4030dp83932State, iobase,         0x80001000),
+        DEFINE_PROP_UINT32("itshift", RC4030dp83932State, state.it_shift, 2),
+        DEFINE_PROP_UINT32("irq",     RC4030dp83932State, irq,            4),
+        DEFINE_NIC_PROPERTIES(        RC4030dp83932State, state.conf),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
+static void dp8393x_register_devices(void)
+{
+    rc4030_qdev_register(&dp83932_rc4030_info);
+}
+
+device_init(dp8393x_register_devices)

index aa790d8..d8e4954 100644
@@ -15,9 +15,4 @@ void ds1225y_set_protection(void *opaque, int protection);
 /* mipsnet.c */
 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
 
-/* dp8393x.c */
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
-                  qemu_irq irq, void* mem_opaque,
-                  void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
-
 #endif

index cf0001e..c0a27b2 100644
@@ -192,8 +192,10 @@ void mips_jazz_init (ram_addr_t ram_size,
         if (!nd->model)
             nd->model = qemu_strdup("dp83932");
         if (strcmp(nd->model, "dp83932") == 0) {
-            dp83932_init(nd, 0x80001000, 2, rc4030[4],
-                         rc4030_opaque, rc4030_dma_memory_rw);
+            qemu_check_nic_model(nd, nd->model);
+            dev = qdev_create(NULL, nd->model);
+            qdev_set_nic_properties(dev, nd);
+            qdev_init_nofail(dev);
             break;
         } else if (strcmp(nd->model, "?") == 0) {
             fprintf(stderr, "qemu: Supported NICs: dp83932\n");

index 2d50bd6..d51a29c 100644
@@ -33,6 +33,7 @@
 #include "qemu-timer.h"
 #include "isa.h"
 #include "sysbus.h"
+#include "rc4030.h"
 #include "qdev-addr.h"
 
 /********************************************************/

@@ -524,6 +525,14 @@ typedef struct FDCtrlISABus {
     struct FDCtrl state;
 } FDCtrlISABus;
 
+typedef struct FDCtrlRC4030 {
+    RC4030Device busdev;
+    target_phys_addr_t iobase;
+    uint32_t irq;
+    uint32_t dma;
+    struct FDCtrl state;
+} FDCtrlRC4030;
+
 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
 {
     FDCtrl *fdctrl = opaque;

@@ -714,6 +723,14 @@ static void fdctrl_external_reset_isa(DeviceState *d)
     fdctrl_reset(s, 0);
 }
 
+static void fdctrl_external_reset_rc4030(DeviceState *d)
+{
+    FDCtrlRC4030 *rc4030 = container_of(d, FDCtrlRC4030, busdev.qdev);
+    FDCtrl *s = &rc4030->state;
+
+    fdctrl_reset(s, 0);
+}
+
 static void fdctrl_handle_tc(void *opaque, int irq, int level)
 {
     //FDCtrl *s = opaque;

@@ -1888,30 +1905,6 @@ FDCtrl *fdctrl_init_isa(DriveInfo **fds)
     return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
 }
 
-FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
-                           target_phys_addr_t mmio_base, DriveInfo **fds)
-{
-    FDCtrl *fdctrl;
-    DeviceState *dev;
-    FDCtrlSysBus *sys;
-
-    dev = qdev_create(NULL, "sysbus-fdc");
-    sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
-    fdctrl = &sys->state;
-    fdctrl->dma_chann = dma_chann; /* FIXME */
-    if (fds[0]) {
-        qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
-    }
-    if (fds[1]) {
-        qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
-    }
-    qdev_init_nofail(dev);
-    sysbus_connect_irq(&sys->busdev, 0, irq);
-    sysbus_mmio_map(&sys->busdev, 0, mmio_base);
-
-    return fdctrl;
-}
-
 FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
                           DriveInfo **fds, qemu_irq *fdc_tc)
 {

@@ -2026,6 +2019,22 @@ static int sun4m_fdc_init1(SysBusDevice *dev)
     return fdctrl_init_common(fdctrl);
 }
 
+static int rc4030_fdc_init1(RC4030Device *dev)
+{
+    FDCtrlRC4030 *rc4030 = DO_UPCAST(FDCtrlRC4030, busdev, dev);
+    FDCtrl *fdctrl = &rc4030->state;
+    int io;
+
+    io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
+    cpu_register_physical_memory(rc4030->iobase, 8, io);
+
+    rc4030_init_irq(dev, &fdctrl->irq, rc4030->irq);
+    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
+    fdctrl->dma_chann = rc4030->dma;
+
+    return fdctrl_init_common(fdctrl);
+}
+
 static const VMStateDescription vmstate_isa_fdc ={
     .name = "fdc",
     .version_id = 2,

@@ -2085,11 +2094,38 @@ static SysBusDeviceInfo sun4m_fdc_info = {
     },
 };
 
+static const VMStateDescription vmstate_rc4030_fdc = {
+    .name = "rc4030-fdc",
+    .version_id = 2,
+    .minimum_version_id = 2,
+    .fields = (VMStateField []) {
+        VMSTATE_STRUCT(state, FDCtrlRC4030, 0, vmstate_fdc, FDCtrl),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static RC4030DeviceInfo rc4030_fdc_info = {
+    .init = rc4030_fdc_init1,
+    .qdev.name = "rc4030-fdc",
+    .qdev.size = sizeof(FDCtrlRC4030),
+    .qdev.vmsd = &vmstate_rc4030_fdc,
+    .qdev.reset = fdctrl_external_reset_rc4030,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_TADDR("iobase", FDCtrlRC4030, iobase, 0x80003000),
+        DEFINE_PROP_UINT32("irq",   FDCtrlRC4030, irq, 1),
+        DEFINE_PROP_UINT32("dma",   FDCtrlRC4030, dma, 0),
+        DEFINE_PROP_DRIVE("driveA", FDCtrlRC4030, state.drives[0].bs),
+        DEFINE_PROP_DRIVE("driveB", FDCtrlRC4030, state.drives[1].bs),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
 static void fdc_register_devices(void)
 {
     isa_qdev_register(&isa_fdc_info);
     sysbus_register_withprop(&sysbus_fdc_info);
     sysbus_register_withprop(&sun4m_fdc_info);
+    rc4030_qdev_register(&rc4030_fdc_info);
 }
 
 device_init(fdc_register_devices)

index b6b3772..6f28dc0 100644
@@ -8,8 +8,6 @@
 typedef struct FDCtrl FDCtrl;
 
 FDCtrl *fdctrl_init_isa(DriveInfo **fds);
-FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
-                           target_phys_addr_t mmio_base, DriveInfo **fds);
 FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
                           DriveInfo **fds, qemu_irq *fdc_tc);
 int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num);

index c0a27b2..3c6a495 100644
@@ -109,7 +109,7 @@ void mips_jazz_init (ram_addr_t ram_size,
     int s_dma_dummy;
     NICInfo *nd;
     PITState *pit;
-    DriveInfo *fds[MAX_FD];
+    DriveInfo *fd;
     qemu_irq esp_reset;
     qemu_irq *cpu_exit_irq;
     ram_addr_t ram_offset;

@@ -216,10 +216,14 @@ void mips_jazz_init (ram_addr_t ram_size,
         fprintf(stderr, "qemu: too many floppy drives\n");
         exit(1);
     }
-    for (n = 0; n < MAX_FD; n++) {
-        fds[n] = drive_get(IF_FLOPPY, 0, n);
+    dev = qdev_create(NULL, "rc4030-fdc");
+    if ((fd = drive_get(IF_FLOPPY, 0, 0)) != NULL) {
+        qdev_prop_set_drive_nofail(dev, "driveA", fd->bdrv);
     }
-    fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
+    if ((fd = drive_get(IF_FLOPPY, 0, 1)) != NULL) {
+        qdev_prop_set_drive_nofail(dev, "driveB", fd->bdrv);
+    }
+    qdev_init_nofail(dev);
 
     /* Real time clock */
     rtc_init(1980, NULL);

index 349052a..d6a9824 100644
@@ -24,6 +24,8 @@
 
 #include "sysbus.h"
 #include "scsi.h"
+#include "rc4030.h"
+#include "qdev-addr.h"
 #include "esp.h"
 
 /* debug ESP card */

@@ -82,6 +84,15 @@ struct ESPState {
     void *dma_opaque;
 };
 
+typedef struct RC4030ESPState
+{
+    RC4030Device dev;
+    target_phys_addr_t iobase;
+    uint32_t irq;
+    uint32_t dma;
+    ESPState state;
+} RC4030ESPState;
+
 #define ESP_TCLO   0x0
 #define ESP_TCMID  0x1
 #define ESP_FIFO   0x2

@@ -356,11 +367,9 @@ static void esp_do_dma(ESPState *s)
     }
 }
 
-static void esp_command_complete(SCSIBus *bus, int reason, uint32_t tag,
-                                 uint32_t arg)
+static void esp_command_complete1(ESPState *s, int reason, uint32_t tag,
+                                  uint32_t arg)
 {
-    ESPState *s = DO_UPCAST(ESPState, busdev.qdev, bus->qbus.parent);
-
     if (reason == SCSI_REASON_DONE) {
         DPRINTF("SCSI Command complete\n");
         if (s->ti_size != 0)

@@ -388,6 +397,20 @@ static void esp_command_complete(SCSIBus *bus, int reason, uint32_t tag,
     }
 }
 
+static void esp_command_complete(SCSIBus *bus, int reason, uint32_t tag,
+                                 uint32_t arg)
+{
+    ESPState *s = DO_UPCAST(ESPState, busdev.qdev, bus->qbus.parent);
+    esp_command_complete1(s, reason, tag, arg);
+}
+
+static void esp_rc4030_command_complete(SCSIBus *bus, int reason,
+                                        uint32_t tag, uint32_t arg)
+{
+    RC4030ESPState *rc4030 = container_of(bus->qbus.parent, RC4030ESPState, dev.qdev);
+    esp_command_complete1(&rc4030->state, reason, tag, arg);
+}
+
 static void handle_ti(ESPState *s)
 {
     uint32_t dmalen, minlen;

@@ -435,6 +458,12 @@ static void esp_hard_reset(DeviceState *d)
     s->rregs[ESP_CFG1] = 7;
 }
 
+static void esp_rc4030_hard_reset(DeviceState *d)
+{
+    RC4030ESPState *s = container_of(d, RC4030ESPState, dev.qdev);
+    esp_hard_reset(&s->state.busdev.qdev);
+}
+
 static void esp_soft_reset(DeviceState *d)
 {
     ESPState *s = container_of(d, ESPState, busdev.qdev);

@@ -682,6 +711,27 @@ static int esp_init1(SysBusDevice *dev)
     return scsi_bus_legacy_handle_cmdline(&s->bus);
 }
 
+static int esp_rc4030_init1(RC4030Device *dev)
+{
+    RC4030ESPState *rc4030 = container_of(dev, RC4030ESPState, dev);
+    ESPState *s = &rc4030->state;
+    int io;
+
+    rc4030_init_irq(&rc4030->dev, &s->irq, rc4030->irq);
+
+    io = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
+    cpu_register_physical_memory(rc4030->iobase, ESP_REGS << s->it_shift, io);
+
+    qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
+
+    s->dma_memory_read = rc4030_dma_read;
+    s->dma_memory_write = rc4030_dma_write;
+    s->dma_opaque = rc4030_get_dma(rc4030->dma);
+
+    scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, esp_rc4030_command_complete);
+    return scsi_bus_legacy_handle_cmdline(&s->bus);
+}
+
 static SysBusDeviceInfo esp_info = {
     .init = esp_init1,
     .qdev.name  = "esp",

@@ -693,9 +743,34 @@ static SysBusDeviceInfo esp_info = {
     }
 };
 
+static const VMStateDescription vmstate_rc4030_esp = {
+    .name = "rc4030-esp",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields      = (VMStateField []) {
+        VMSTATE_STRUCT(state, RC4030ESPState, 0, vmstate_esp, ESPState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static RC4030DeviceInfo esp_rc4030_info = {
+    .qdev.name  = "rc4030-esp",
+    .qdev.size  = sizeof(RC4030ESPState),
+    .qdev.vmsd  = &vmstate_rc4030_esp,
+    .qdev.reset = esp_rc4030_hard_reset,
+    .init       = esp_rc4030_init1,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_TADDR("iobase", RC4030ESPState, iobase, 0x80002000),
+        DEFINE_PROP_UINT32("irq",   RC4030ESPState, irq,    5),
+        DEFINE_PROP_UINT32("dma",   RC4030ESPState, dma,    0),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
 static void esp_register_devices(void)
 {
     sysbus_register_withprop(&esp_info);
+    rc4030_qdev_register(&esp_rc4030_info);
 }
 
 device_init(esp_register_devices)

index 3c6a495..08175ab 100644
@@ -110,7 +110,6 @@ void mips_jazz_init (ram_addr_t ram_size,
     NICInfo *nd;
     PITState *pit;
     DriveInfo *fd;
-    qemu_irq esp_reset;
     qemu_irq *cpu_exit_irq;
     ram_addr_t ram_offset;
     ram_addr_t bios_offset;

@@ -207,9 +206,7 @@ void mips_jazz_init (ram_addr_t ram_size,
     }
 
     /* SCSI adapter */
-    esp_init(0x80002000, 0,
-             rc4030_dma_read, rc4030_dma_write, dmas[0],
-             rc4030[5], &esp_reset);
+    rc4030_create_simple("rc4030-esp");
 
     /* Floppy */
     if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {

index 009d127..afbfcb0 100644
@@ -25,15 +25,20 @@
 #include "hw.h"
 #include "mips.h"
 #include "nvram.h"
+#include "sysbus.h"
+#include "qdev-addr.h"
 
 //#define DEBUG_NVRAM
 
 typedef struct ds1225y_t
 {
-    uint32_t chip_size;
+    SysBusDevice busdev;
+
+    target_phys_addr_t iobase;
+    uint32_t size;
+    char *filename;
     QEMUFile *file;
     uint8_t *contents;
-    uint8_t protection;
 } ds1225y_t;
 
 

@@ -98,34 +103,6 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
     nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
 }
 
-static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    ds1225y_t *s = opaque;
-
-    if (s->protection != 7) {
-#ifdef DEBUG_NVRAM
-    printf("nvram: prevent write of 0x%x at " TARGET_FMT_lx "\n", val, addr);
-#endif
-        return;
-    }
-
-    nvram_writeb(opaque, addr, val);
-}
-
-static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    nvram_writeb_protected(opaque, addr, val & 0xff);
-    nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
-}
-
-static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    nvram_writeb_protected(opaque, addr, val & 0xff);
-    nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
-    nvram_writeb_protected(opaque, addr + 2, (val >> 16) & 0xff);
-    nvram_writeb_protected(opaque, addr + 3, (val >> 24) & 0xff);
-}
-
 static CPUReadMemoryFunc * const nvram_read[] = {
     &nvram_readb,
     &nvram_readw,

@@ -138,43 +115,75 @@ static CPUWriteMemoryFunc * const nvram_write[] = {
     &nvram_writel,
 };
 
-static CPUWriteMemoryFunc * const nvram_write_protected[] = {
-    &nvram_writeb_protected,
-    &nvram_writew_protected,
-    &nvram_writel_protected,
-};
-
-/* Initialisation routine */
-void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
+static int ds1225y_init(SysBusDevice *dev)
 {
-    ds1225y_t *s;
-    int mem_indexRW, mem_indexRP;
+    ds1225y_t *s = FROM_SYSBUS(ds1225y_t, dev);
+    int mem_index;
     QEMUFile *file;
 
-    s = qemu_mallocz(sizeof(ds1225y_t));
-    s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
-    s->contents = qemu_mallocz(s->chip_size);
-    s->protection = 7;
-
-    /* Read current file */
-    file = qemu_fopen(filename, "rb");
-    if (file) {
-        /* Read nvram contents */
-        qemu_get_buffer(file, s->contents, s->chip_size);
-        qemu_fclose(file);
-    }
-    s->file = qemu_fopen(filename, "wb");
-    if (s->file) {
-        /* Write back contents, as 'wb' mode cleaned the file */
-        qemu_put_buffer(s->file, s->contents, s->chip_size);
-        qemu_fflush(s->file);
+    if (s->iobase == -1)
+      return -1;
+
+    s->contents = qemu_mallocz(s->size);
+
+    if (s->filename) {
+        /* Read current file */
+        file = qemu_fopen(s->filename, "rb");
+        if (file) {
+            /* Read nvram contents */
+            qemu_get_buffer(file, s->contents, s->size);
+            qemu_fclose(file);
+        }
+        s->file = qemu_fopen(s->filename, "wb");
+        if (s->file) {
+            /* Write back contents, as 'wb' mode cleaned the file */
+            qemu_put_buffer(s->file, s->contents, s->size);
+            qemu_fflush(s->file);
+        }
     }
 
-    /* Read/write memory */
-    mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s);
-    cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
-    /* Read/write protected memory */
-    mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s);
-    cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP);
-    return s;
+    mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
+    cpu_register_physical_memory(s->iobase, s->size, mem_index);
+
+    return 0;
+}
+
+static int ds1225y_init_nvram(SysBusDevice *dev)
+{
+  ds1225y_t *s = FROM_SYSBUS(ds1225y_t, dev);
+  s->filename = (char*)"nvram";
+  return ds1225y_init(dev);
+}
+
+static SysBusDeviceInfo ds1225y_device_info = {
+    .qdev.name  = "ds1225y",
+    .qdev.size  = sizeof(ds1225y_t),
+    .init       = ds1225y_init,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_TADDR("iobase", ds1225y_t, iobase, -1),
+        DEFINE_PROP_HEX32("size", ds1225y_t, size, 0x2000),
+        DEFINE_PROP_STRING("filename", ds1225y_t, filename),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
+static SysBusDeviceInfo ds1225y_device_info_nvram = {
+    .qdev.name    =   "ds1225y,filename=nvram",
+    .qdev.size    = sizeof(ds1225y_t),
+    .qdev.no_user = 1,
+    .init         = ds1225y_init_nvram,
+    .qdev.props   = (Property[]) {
+        DEFINE_PROP_TADDR("iobase", ds1225y_t, iobase, 0x80009000),
+        DEFINE_PROP_HEX32("size", ds1225y_t, size, 0x2000),
+        DEFINE_PROP_STRING("filename", ds1225y_t, filename),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
+static void ds1225y_register_devices(void)
+{
+    sysbus_register_withprop(&ds1225y_device_info);
+    sysbus_register_withprop(&ds1225y_device_info_nvram);
 }
+
+device_init(ds1225y_register_devices)

index d8e4954..5d59b1e 100644
@@ -8,10 +8,6 @@ PCIBus *pci_gt64120_init(qemu_irq *pic);
 /* bonito.c */
 PCIBus *bonito_init(qemu_irq *pic);
 
-/* ds1225y.c */
-void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
-void ds1225y_set_protection(void *opaque, int protection);
-
 /* mipsnet.c */
 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
 

index 08175ab..6daf76e 100644
@@ -247,8 +247,9 @@ void mips_jazz_init (ram_addr_t ram_size,
     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
     audio_init(i8259);
 
-    /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
-    ds1225y_init(0x80009000, "nvram");
+    /* NVRAM */
+    dev = qdev_create(NULL, "ds1225y,filename=nvram");
+    qdev_init_nofail(dev);
 
     /* LED indicator */
     dev = qdev_create(NULL, "jazz-led");

index 6daf76e..b4c95c9 100644
@@ -37,6 +37,7 @@
 #include "loader.h"
 #include "mc146818rtc.h"
 #include "rc4030.h"
+#include "sysbus.h"
 
 enum jazz_model_e
 {

@@ -274,6 +275,14 @@ void mips_pica61_init (ram_addr_t ram_size,
     mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
 }
 
+static
+void empty_init (ram_addr_t ram_size,
+                 const char *boot_device,
+                 const char *kernel_filename, const char *kernel_cmdline,
+                 const char *initrd_filename, const char *cpu_model)
+{
+}
+
 static QEMUMachine mips_magnum_machine = {
     .name = "magnum",
     .desc = "MIPS Magnum",

@@ -288,10 +297,79 @@ static QEMUMachine mips_pica61_machine = {
     .use_scsi = 1,
 };
 
+static QEMUMachine empty_machine = {
+    .name = "empty",
+    .desc = "Empty machine",
+    .init = empty_init,
+};
+
 static void mips_jazz_machine_init(void)
 {
     qemu_register_machine(&mips_magnum_machine);
     qemu_register_machine(&mips_pica61_machine);
+    qemu_register_machine(&empty_machine);
 }
 
 machine_init(mips_jazz_machine_init);
+
+typedef struct MipsBoardState {
+    SysBusDevice busdev;
+
+    char *romfile;
+    uint32_t romsize;
+    uint32_t ramsize;
+} MipsBoardState;
+
+static int mips_board_device_init(SysBusDevice *dev)
+{
+    MipsBoardState *s = FROM_SYSBUS(MipsBoardState, dev);
+    int bios_size;
+    ram_addr_t ram_size;
+    ram_addr_t ram_offset;
+    ram_addr_t bios_offset;
+
+    /* allocate RAM */
+    ram_size = s->ramsize * 1024 * 1024;
+    ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size);
+    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+
+    /* load the BIOS image */
+    if (s->romfile) {
+        bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", s->romsize);
+        cpu_register_physical_memory(0x1fc00000LL,
+                                     s->romsize, bios_offset | IO_MEM_ROM);
+        cpu_register_physical_memory(0xfff00000LL,
+                                     s->romsize, bios_offset | IO_MEM_ROM);
+
+        bios_size = load_image_targphys(s->romfile,
+                                        0x1fc00000LL,
+                                        s->romsize);
+
+        bios_size = load_image_targphys(s->romfile,
+                                        0xfff00000LL,
+                                        s->romsize);
+        if (bios_size != s->romsize) {
+            return -1;
+        }
+    }
+    return 0;
+}
+
+static SysBusDeviceInfo board_device_info = {
+    .qdev.name = "mips-board",
+    .qdev.size = sizeof(MipsBoardState),
+    .init      = mips_board_device_init,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_STRING("romfile", MipsBoardState, romfile),
+        DEFINE_PROP_HEX32("romsize", MipsBoardState, romsize, 0x40000),
+        DEFINE_PROP_UINT32("ramsize", MipsBoardState, ramsize, 64),
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
+static void mips_register_devices(void)
+{
+    sysbus_register_withprop(&board_device_info);
+}
+
+device_init(mips_register_devices)

index e99c73f..f907385 100644
@@ -455,6 +455,12 @@ static BusState *qbus_find_recursive(BusState *bus, const char *name,
     BusState *child, *ret;
     int match = 1;
 
+    if (!bus) {
+        if (!main_system_bus) {
+            main_system_bus = qbus_create(&system_bus_info, NULL, "main-system-bus");
+        }
+        return main_system_bus;
+    }
     if (name && (strcmp(bus->name, name) != 0)) {
         match = 0;
     }

index b4c95c9..04d80ee 100644
@@ -104,9 +104,7 @@ void mips_jazz_init (ram_addr_t ram_size,
     int bios_size, n;
     BusState *cpu;
     DeviceState *dev;
-    qemu_irq *rc4030, *i8259;
-    rc4030_dma *dmas;
-    void* rc4030_opaque;
+    qemu_irq *i8259;
     int s_dma_dummy;
     NICInfo *nd;
     PITState *pit;

@@ -158,7 +156,8 @@ void mips_jazz_init (ram_addr_t ram_size,
     }
 
     /* Chipset */
-    rc4030_opaque = rc4030_init(cpu, &rc4030, &dmas);
+    dev = qdev_create(cpu, "rc4030");
+    qdev_init_nofail(dev);
     s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 

index 3c8cdfa..710085e 100644
@@ -948,20 +948,3 @@ static void rc4030_register_devices(void)
 
 device_init(rc4030_register_devices)
 
-void *rc4030_init(BusState *bus,
-                  qemu_irq **irqs, rc4030_dma **dmas)
-{
-    DeviceState *dev;
-    rc4030State* rc4030;
-
-    dev = qdev_create(bus, "rc4030");
-    qdev_init_nofail(dev);
-
-    rc4030 = DO_UPCAST(rc4030State, busdev, dev);
-
-    *irqs = rc4030->busdev.gpio_in;
-    *dmas = rc4030->bus.dmas;
-
-    return rc4030;
-}
-

index 58522f3..f15b459 100644
@@ -34,8 +34,4 @@ void rc4030_dma_write(void *dma, uint8_t *buf, int len);
 void *rc4030_get_opaque(void);
 rc4030_dma rc4030_get_dma(int dma);
 
-/* Non-qdev compatibility stuff... */
-void *rc4030_init(BusState *parent,
-                  qemu_irq **irqs, rc4030_dma **dmas);
-
 #endif