m68knommu: added dm9000 support

RFC PATCH Superseded Angelo Dureghello 2 participants 2 messages Jan 5, 2011

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Angelo Dureghello

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2011-01-05 16:48 UTC #0 lore raw

RFC PATCH 1/1 m68knommu: added dm9000 support

This patch allows to use the dm9000 network chip with a m68knommu big-endian cpu. From the HW point of view, the cpu data bus connected to the dm9000 chip should be hardware-byte-swapped, crossing the bytes wires (D0:7 to D24:31, etc.). In anyway, has been also added an option to swap the bytes in the driver, if some cpu has been wired straight D0:D31 to dm9000.

Signed-off-by Angelo Dureghello <[email protected]>

---

net/Kconfig 2011-01-04 22:33:14.132301872 +0100 renamed from net/Kconfig.orig 2011-01-05 17:11:37.992376124 +0100 +9 -2

@@ -960,7 +960,7 @@ config TI_DAVINCI_EMAC
 
 config DM9000
   tristate "DM9000 support"
-  depends on ARM || BLACKFIN || MIPS
+  depends on COLDFIRE || ARM || BLACKFIN || MIPS
   select CRC32
   select MII
   ---help---

@@ -986,6 +986,14 @@ config DM9000_FORCE_SIMPLE_PHY_POLL
     costly MII PHY reads. Note, this will not work if the chip is
     operating with an external PHY.
 
+config DM9000_32BIT_SW_SWAP
+  bool "Software byte swap for 32 bit data bus"
+  depends on DM9000 && COLDFIRE
+  ---help---
+    This configuration allows to swap data bytes from the dm9000
+    driver itself, when the big endian cpu is wired straight to
+    the dm9000 32 bit data bus.
+
 config ENC28J60
   tristate "ENC28J60 support"
   depends on EXPERIMENTAL && SPI && NET_ETHERNET

@@ -3347,4 +3355,3 @@ config VMXNET3
          module will be called vmxnet3.
 
 endif # NETDEVICES
-

net/dm9000.c 2011-01-05 16:30:48.636116500 +0100 renamed from net/dm9000.c.orig 2010-12-30 23:19:39.747836070 +0100 +97 ~~-12~~

252 lines not on this page · raw message

write command */

+#ifdef CONFIG_DM9000_32BIT_SW_SWAP
+ writel(reg_save, db->io_addr);
+#else

     writeb(reg_save, db->io_addr);
+#endif
+
     spin_unlock_irqrestore(&db->lock, flags);

     dm9000_msleep(db, 1);        /* Wait write complete */

     spin_lock_irqsave(&db->lock,flags);

- reg_save = readb(db->io_addr);
+#ifdef CONFIG_DM9000_32BIT_SW_SWAP
+ reg_save = (u8)readl(db->io_addr);
+#else
+ reg_save = readb(db->io_addr);
+#endif

     iow(db, DM9000_EPCR, 0x0);    /* Clear phyxcer write command */

     /* restore the previous address */
+#ifdef CONFIG_DM9000_32BIT_SW_SWAP
+    writel(reg_save, db->io_addr);
+#else
     writeb(reg_save, db->io_addr);

+#endif

     spin_unlock_irqrestore(&db->lock, flags);
     mutex_unlock(&db->addr_lock);

@@ -1713,4 +1811,3 @@ MODULE_AUTHOR("Sascha Hauer, Ben Dooks")
MODULE_DESCRIPTION("Davicom DM9000 network driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:dm9000");
-

m68k/include/asm/io_no.h 2011-01-04 23:45:08.893049554 +0100 renamed from m68k/include/asm/io_no.h.orig 2011-01-05 16:53:55.904905038 +0100 +85 -1

95 lines not on this page · raw message

Randy Dunlap

2011-01-05 16:59 UTC #1 lore raw

net/Kconfig 2011-01-04 22:33:14.132301872 +0100

Quoted 12 lines · On Wed, 05 Jan 2011 17:48:36 +0100 Angelo Dureghello wrote:

This patch allows to use the dm9000 network chip with a m68knommu big-endian cpu. From the HW point of view, the cpu data bus connected to the dm9000 chip should be hardware-byte-swapped, crossing the bytes wires (D0:7 to D24:31, etc.). In anyway, has been also added an option to swap the bytes in the driver, if some cpu has been wired straight D0:D31 to dm9000.
Signed-off-by Angelo Dureghello <[email protected]>
---
net/Kconfig 2011-01-04 22:33:14.132301872 +0100 renamed from net/Kconfig.orig 2011-01-05 17:11:37.992376124 +0100 +0 -0

File names should begin at top level of linux kernel source tree, like this e.g.:

drivers/net/Kconfig 2011-01-04 22:33:14.132301872 +0100 config TI_DAVINCI_EMAC · line 966

Quoted 13 lines

drivers/net/Kconfig 2011-01-04 22:33:14.132301872 +0100 renamed from drivers/net/Kconfig.orig 2011-01-05 17:11:37.992376124 +0100 +1 -1
@@ -960,7 +960,7 @@ config TI_DAVINCI_EMAC
 
  config DM9000
    tristate "DM9000 support"
-  depends on ARM || BLACKFIN || MIPS
+  depends on COLDFIRE || ARM || BLACKFIN || MIPS
    select CRC32
    select MII
    ---help---

Something has modified tab(s) to spaces in this patch, so the patch won't apply cleanly. See if Documentation/email-clients.txt can help you.

Oh, are you using the gmail web-based email client? That won't work for kernel patches. You could use gmail via SMTP.

Quoted 5 lines

drivers/net/Kconfig 2011-01-04 22:33:14.132301872 +0100 renamed from drivers/net/Kconfig.orig 2011-01-05 17:11:37.992376124 +0100 +1 -0
@@ -986,6 +986,14 @@ config DM9000_FORCE_SIMPLE_PHY_POLL
      costly MII PHY reads. Note, this will not work if the chip is
      operating with an external PHY.
 
+config DM9000_32BIT_SW_SWAP

drivers/net/Kconfig 2011-01-04 22:33:14.132301872 +0100 config DM9000_FORCE_SIMPLE_PHY_POLL · line 999

Quoted 10 lines

drivers/net/Kconfig 2011-01-04 22:33:14.132301872 +0100 renamed from drivers/net/Kconfig.orig 2011-01-05 17:11:37.992376124 +0100 +7 -0

+  bool "Software byte swap for 32 bit data bus"
+  depends on DM9000 && COLDFIRE
+  ---help---
+    This configuration allows to swap data bytes from the dm9000
+    driver itself, when the big endian cpu is wired straight to
+    the dm9000 32 bit data bus.
+
  config ENC28J60
    tristate "ENC28J60 support"
    depends on EXPERIMENTAL && SPI && NET_ETHERNET

---
~Randy
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