Pull Request

Dear Wolfgang,

The following changes since commit 8d4addc3c3fe1a9ea160a5a1a20a1f934ff3fe97:
Wolfgang Denk (1):
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

are available in the git repository at:

git://git.denx.de/u-boot-nios.git next

Thomas Chou (4):
nios2: add gpio_free
altera_spi: add spi_set_speed
nios2: use long for ssize_t
nios2: add gpio_is_valid

  arch/nios2/include/asm/gpio.h            |   12 ++++++++++++
  arch/nios2/include/asm/posix_types.h     |    2 +-
  board/altera/nios2-generic/custom_fpga.h |    1 +
  board/altera/nios2-generic/gpio.c        |   11 +++++++++++
  drivers/spi/altera_spi.c                 |    5 +++++
  5 files changed, 30 insertions(+), 1 deletions(-)

We have a system with a P1022 connected to a 5461S in SGMII mode.

In order to make it work in SGMII mode, I set TBI ANA to 0x4001 as per AN3869. Note that those bit are described as reserved in the P1022 doc that I have.
I was then able to transfer data at 100/1000 (10 not tested).

As per AN3869 a value of 0x1a0 is for 1000BASE-X.

Looking at the tsec driver (drivers/net/tsec.c), one can see:

#define TBIANA_SETTINGS ( \
          TBIANA_ASYMMETRIC_PAUSE \
          | TBIANA_SYMMETRIC_PAUSE \
          | TBIANA_FULL_DUPLEX \
          )

==> 0x1a0

if (regs->ecntrl& ECNTRL_SGMII_MODE)

          tsec_configure_serdes(priv);

That would mean the TBI ANA is not set correctly when SGMII is reported.

Please can you verify this.

Cheers.

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We have a system with a P1022 connected to a 5461S in SGMII mode.

In order to make it work in SGMII mode, I set TBI ANA to 0x4001 as per AN3869. Note that those bit are described as reserved in the P1022 doc that I have.
I was then able to transfer data at 100/1000 (10 not tested).

As per AN3869 a value of 0x1a0 is for 1000BASE-X.

Looking at the tsec driver (drivers/net/tsec.c), one can see:

#define TBIANA_SETTINGS ( \
         TBIANA_ASYMMETRIC_PAUSE \
         | TBIANA_SYMMETRIC_PAUSE \
         | TBIANA_FULL_DUPLEX \
         )

==> 0x1a0

if (regs->ecntrl & ECNTRL_SGMII_MODE)

         tsec_configure_serdes(priv);

That would mean the TBI ANA is not set correctly when SGMII is reported.

Please can you verify this.

Hi Renaud,

Quoted 19 lines · Renaud Barbier

We have a system with a P1022 connected to a 5461S in SGMII mode.

In order to make it work in SGMII mode, I set TBI ANA to 0x4001 as per AN3869. Note that those bit are described as reserved in the P1022 doc that I have.
I was then able to transfer data at 100/1000 (10 not tested).

As per AN3869 a value of 0x1a0 is for 1000BASE-X.

Looking at the tsec driver (drivers/net/tsec.c), one can see:

#define TBIANA_SETTINGS ( \
          TBIANA_ASYMMETRIC_PAUSE \
          | TBIANA_SYMMETRIC_PAUSE \
          | TBIANA_FULL_DUPLEX \
          )

==> 0x1a0

Quoted 7 lines

if (regs->ecntrl& ECNTRL_SGMII_MODE)

          tsec_configure_serdes(priv);

That would mean the TBI ANA is not set correctly when SGMII is reported.

Please can you verify this.

Gotta love those undocumented register bits:) This same issue has been discussed a number of times, but no one ever noticed the 0x4001 in AN3869, or assumed it was an error. The bug also didn't seem to affect some PHYs, eg Vitesse models:

http://old.nabble.com/-U-Boot---PATCH--tsec:-Force-TBI-PHY-to-1000Mbps-full-duplex-in-SGMII-mode-td26188785.html
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/89059
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/80256

My company worked around the issue by not enabling auto-negotiation in the TBI control register via a custom CONFIG_TSEC_TBICR_SETTINGS value. I just tried removing our workaround and setting TBIANA_SETTINGS to 0x4001, and it looks like it works on a P2020-based board with a BCM5482S PHY.

It'd be ideal if someone from from Freescale chimed in so we knew what bits we were hitting in the TBIANA register. The change has my ack though. Let me know if you don't plan on submitting a change and I'll update our boards, as well as the value of TBIANA_SETTINGS.

Best,
Peter