Big endian support for RV730

PATCH In review Cédric Cano 2 participants 4 messages Feb 11, 2011

Subsystems (2)

DRM drivers Radeon and amdgpu DRM drivers

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Cédric Cano

author

2011-02-11 10:32 UTC #0 lore raw

PATCH 1/1 Big endian support for RV730

Here are a couple of patches that enable support for RV730 on big endian architectures. The following items will work :
* KMS
- correct color in framebuffer
- interrupts
- kms blit
- power management
* DDX
- kms enabled
- exa
- video textures
- hardware cursor

For the BE modifications, the AMD Linux Engineering team advised me to focus on :
- make sure all the atombios data table accesses are endian safe
- set the display controller swappers properly(http://lists.freedesktop.org/archives/dri-devel/2011-January/007486.html)
- make sure the appropriate endian swapper is enabled in the texture and vertex fetch constants (see SQ_TEX_RESOURCE_WORD* and SQ_VTX_RESOURCE_WORD* regs)
- make sure the shaders are stored in LE order
- make sure shader constant buffers are stored in LE order
- endian swap IH (interrupt handler) packets
- endian swap the CP command buffers
- endian swap WB (write back) buffers

That's what I tried to do and so far, I have KMS and DDX (with EXA) drivers working. Drivers have been tested on a MPC8640 custom design, with a custom graphics board based on E4690 (RV730). I'm using a custom linux distribution with Xorg 7.6 (xf86-video-ati 6.13.2). The latest kernel available for my board is 2.6.35.6 so I haven't tested with upstream kernel.

I'd also like to test more the ddx driver in order to check the EXA functions do a correct rendering. Is there a driver framework testing, or some kind of unit test you, ddx driver writers, are using ?

Regards,
Cedric Cano

Cédric Cano

author

2011-02-11 10:38 UTC #1 lore raw

Signed-off-by Cedric Cano <ccano at interfaceconcept.com>

---

src/drmmode_display.c 2011-02-10 14:27:56.000000000 +0100 renamed from src/drmmode_display.c 2010-09-28 00:20:53.000000000 +0200 +6 -3

diff -Naur xf86-video-ati-6.13.2/src/drmmode_display.c xf86-video-ati-6.13.2/src/drmmode_display.c
@@ -385,12 +385,15 @@
 drmmode_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
 {
     drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
-    void *ptr;
+    int i;
+    uint32_t *ptr;
 
     /* cursor should be mapped already */
-    ptr = drmmode_crtc->cursor_bo->ptr;
+    ptr = (uint32_t *)(drmmode_crtc->cursor_bo->ptr);
 
-    memcpy (ptr, image, 64 * 64 * 4);
+    for(i = 0; i < 64 * 64; i++) {
+        ptr[i] = cpu_to_le32(image[i]);
+    }
 
     return;
 }

src/r600_exa.c 2011-02-10 14:29:03.000000000 +0100 renamed from src/r600_exa.c 2010-09-28 00:20:53.000000000 +0200 +30 -1

diff -Naur xf86-video-ati-6.13.2/src/r600_exa.c xf86-video-ati-6.13.2/src/r600_exa.c
@@ -247,9 +247,15 @@
     } else if (accel_state->dst_obj.bpp == 16) {
     cb_conf.format = COLOR_5_6_5;
     cb_conf.comp_swap = 2; /* RGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+    cb_conf.endian = ENDIAN_8IN16;
+#endif
     } else {
     cb_conf.format = COLOR_8_8_8_8;
     cb_conf.comp_swap = 1; /* ARGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+    cb_conf.endian = ENDIAN_8IN32;
+#endif
     }
     cb_conf.source_format = 1;
     cb_conf.blend_clamp = 1;

@@ -942,7 +948,18 @@
     tex_res.bo                  = accel_state->src_obj[unit].bo;
     tex_res.mip_bo              = accel_state->src_obj[unit].bo;
     tex_res.request_size        = 1;
-
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+    switch(accel_state->src_obj[unit].bpp) {
+    case 16:
+        tex_res.endian = SQ_ENDIAN_8IN16;
+        break;
+    case 32:
+        tex_res.endian = SQ_ENDIAN_8IN32;
+        break;
+    default :
+        break;
+    }
+#endif
     /* component swizzles */
     switch (pPict->format) {
     case PICT_a1r5g5b5:

@@ -1405,6 +1422,18 @@
     }
     cb_conf.source_format = 1;
     cb_conf.blend_clamp = 1;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+    switch(dst_obj.bpp) {
+    case 16:
+        cb_conf.endian = ENDIAN_8IN16;
+        break;
+    case 32:
+        cb_conf.endian = ENDIAN_8IN32;
+        break;
+    default:
+        break;
+    }
+#endif
     set_render_target(pScrn, accel_state->ib, &cb_conf,

accel_state->dst_obj.domain);

     BEGIN_BATCH(24);
@@ -2116,6 +2145,15 @@
     accel_state->xv_ps_offset = 3584;
     R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);

+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {
+ int i;
+ for(i = 0; i < (4096 / 4); i++) {
+ shader[i] = cpu_to_le32(shader[i]);
+ }
+ }
+#endif
+
#ifdef XF86DRM_MODE

 #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4)
     if (info->cs) {

src/r600_shader.c 2011-02-10 14:30:10.000000000 +0100 renamed from src/r600_shader.c 2010-09-28 00:20:53.000000000 +0200 +15 -3

diff -Naur xf86-video-ati-6.13.2/src/r600_shader.c xf86-video-ati-6.13.2/src/r600_shader.c
@@ -111,7 +111,11 @@
                  FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
                  SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
     shader[i++] = VTX_DWORD2(OFFSET(0),
-                 ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+                 ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+                 ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
                  CONST_BUF_NO_STRIDE(0),
                  MEGA_FETCH(1));
     shader[i++] = VTX_DWORD_PAD;

@@ -341,7 +345,11 @@
                  FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
                  SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
     shader[i++] = VTX_DWORD2(OFFSET(0),
-                 ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+                 ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+                 ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
                  CONST_BUF_NO_STRIDE(0),
                  MEGA_FETCH(1));
     shader[i++] = VTX_DWORD_PAD;

@@ -366,7 +374,11 @@
                  FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
                  SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
     shader[i++] = VTX_DWORD2(OFFSET(8),
-                 ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+                 ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+                 ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
                  CONST_BUF_NO_STRIDE(0),
                  MEGA_FETCH(0));
     shader[i++] = VTX_DWORD_PAD;

@@ -596,7 +608,11 @@
                                  FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),

SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
     shader[i++] = VTX_DWORD2(OFFSET(0),