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ColdFire: Queued SPI driver

PATCH Superseded Richard Retanubun 1 participant 1 message Mar 1, 2011

Subsystems (2)
SPI m68k architecture

v1 of 2 Superseded Latest is v2 →

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Richard Retanubun

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PATCH 1/3 ColdFire: Queued SPI driver

Hi TC,

I realize you are not the uboot-coldfire maintainer anymore, but I hope you can help. I posted this patch about 3 weeks ago, just wondering if I used
the wrong e-mail for the uboot coldfire maintainer.

- Richard

< Original email >

-------- Original Message --------
Subject: [PATCH 1/3] ColdFire: Queued SPI driver
Date: Thu, 3 Feb 2011 10:50:22 -0500
From: Richard Retanubun <[email protected]>
To: u-boot at lists.denx.de <[email protected]>
CC: R64188 at freescale.com <[email protected]>, Richard Retanubun <[email protected]>

This patch adds a driver for Freescale Colfire Queued SPI bus. Coded to work with 8 bits per transfer to use with SPI flash. CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.

Tested with MCF5270 which have 4 chip selects.

Activate by #define CONFIG_CF_QSPI in board config.

---
  arch/m68k/cpu/mcf52x2/cpu_init.c      |  134 +++++++++++++++++-
  arch/m68k/include/asm/coldfire/qspi.h |    2 +-
  arch/m68k/include/asm/m5271.h         |   26 ++++
  drivers/spi/Makefile                  |    1 +
  drivers/spi/cf_qspi.c                 |  257 +++++++++++++++++++++++++++++++++
  5 files changed, 418 insertions(+), 2 deletions(-)

create mode 100644 drivers/spi/cf_qspi.c

arch/m68k/cpu/mcf52x2/cpu_init.c +133 -1
index 170bbfc..6dbf5b2 100644
@@ -332,7 +332,139 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
         return 0;
  }
  #endif                         /* CONFIG_CMD_NET */
-#endif
+
+#if defined(CONFIG_CF_QSPI)
+
+/* Configure PIOs for SIN, SOUT, and SCK */
+void cfspi_port_conf(void)
+{
+       mbar_writeByte(MCF_GPIO_PAR_QSPI,
+                      MCF_GPIO_PAR_QSPI_SIN_SIN   |
+                      MCF_GPIO_PAR_QSPI_SOUT_SOUT |
+                      MCF_GPIO_PAR_QSPI_SCK_SCK);
+}
+
+/* Assert chip select, val = [1|0] , dir = out, mode = GPIO */
+void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high)
+{
+       debug("%s: bus %d cs %d cs_active_high %d\n",
+               __func__, bus, cs, cs_active_high);
+
+       switch (cs) {
+       case 0: /* QSPI_CS[0] = PQSPI[3] */
+               if (cs_active_high)
+                       mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
+               else
+                       mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
+
+               mbar_writeByte(MCF_GPIO_PDDR_QSPI,
+                       mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x08);
+
+               mbar_writeByte(MCF_GPIO_PAR_QSPI,
+                       mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
+               break;
+       case 1: /* QSPI_CS[1] = PQSPI[4] */
+               if (cs_active_high)
+                       mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
+               else
+                       mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
+
+               mbar_writeByte(MCF_GPIO_PDDR_QSPI,
+                       mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x10);
+
+               mbar_writeByte(MCF_GPIO_PAR_QSPI,
+                       mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
+               break;
+       case 2: /* QSPI_CS[2] = PTIMER[7] */
+               if (cs_active_high)
+                       mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
+               else
+                       mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
+
+               mbar_writeByte(MCF_GPIO_PDDR_TIMER,
+                       mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x80);
+
+               mbar_writeShort(MCF_GPIO_PAR_TIMER,
+                       mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
+               break;
+       case 3: /* QSPI_CS[3] = PTIMER[3] */
+               if (cs_active_high)
+                       mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
+               else
+                       mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
+
+               mbar_writeByte(MCF_GPIO_PDDR_TIMER,
+                       mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x08);
+
+               mbar_writeShort(MCF_GPIO_PAR_TIMER,
+                       mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
+               break;
+       }
+}
+
+/* Deassert chip select, val = [1|0], dir = in, mode = GPIO
+ * direction set as IN to undrive the pin, external pullup/pulldown will bring
+ * bus to deassert state.
+ */
+void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high)
+{
+       debug("%s: bus %d cs %d cs_active_high %d\n",
+               __func__, bus, cs, cs_active_high);
+
+       switch (cs) {
+       case 0: /* QSPI_CS[0] = PQSPI[3] */
+               if (cs_active_high)
+                       mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
+               else
+                       mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
+
+               mbar_writeByte(MCF_GPIO_PDDR_QSPI,
+                       mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xF7);
+
+               mbar_writeByte(MCF_GPIO_PAR_QSPI,
+                       mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
+               break;
+       case 1: /* QSPI_CS[1] = PQSPI[4] */
+               if (cs_active_high)
+                       mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
+               else
+                       mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
+
+               mbar_writeByte(MCF_GPIO_PDDR_QSPI,
+                       mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xEF);
+
+               mbar_writeByte(MCF_GPIO_PAR_QSPI,
+                       mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
+               break;
+       case 2: /* QSPI_CS[2] = PTIMER[7] */
+               if (cs_active_high)
+                       mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
+               else
+                       mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
+
+               mbar_writeByte(MCF_GPIO_PDDR_TIMER,
+                       mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0x7F);
+
+               mbar_writeShort(MCF_GPIO_PAR_TIMER,
+                       mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
+               break;
+       case 3: /* QSPI_CS[3] = PTIMER[3] */
+               if (cs_active_high)
+                       mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
+               else
+                       mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
+
+               mbar_writeByte(MCF_GPIO_PDDR_TIMER,
+                       mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0xF7);
+
+               mbar_writeShort(MCF_GPIO_PAR_TIMER,
+                       mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
+               break;
+       }
+}
+#endif                         /* CONFIG_CF_QSPI */
+
+#endif                         /* CONFIG_M5271 */
 
  #if defined(CONFIG_M5272)
  /*
arch/m68k/include/asm/coldfire/qspi.h +1 -1
index 8bcd2e4..9fd98f6 100644
@@ -98,7 +98,7 @@ typedef struct qspi_ctrl {
  #define QSPI_QAR_RECV                  (0x0010)
  #define QSPI_QAR_CMD                   (0x0020)
 
-/* DR */
+/* DR with RAM command word definitions */
  #define QSPI_QDR_CONT                  (0x8000)
  #define QSPI_QDR_BITSE                 (0x4000)
  #define QSPI_QDR_DT                    (0x2000)
arch/m68k/include/asm/m5271.h +26 -0
index d25261b..b2bc051 100644
@@ -171,6 +171,32 @@
  #define MCF_GPIO_PAR_UART_U1RXD_UART1          0x0C00
  #define MCF_GPIO_PAR_UART_U1TXD_UART1          0x0300
 
+/* Bit definitions and macros for PAR_QSPI */
+#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK          0x3F
+#define MCF_GPIO_PAR_QSPI_PCS1_PCS1            0xC0
+#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE      0x80
+#define MCF_GPIO_PAR_QSPI_PCS1_GPIO            0x00
+#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK          0xDF
+#define MCF_GPIO_PAR_QSPI_PCS0_PCS0            0x20
+#define MCF_GPIO_PAR_QSPI_PCS0_GPIO            0x00
+#define MCF_GPIO_PAR_QSPI_SIN_UNMASK           0xE7
+#define MCF_GPIO_PAR_QSPI_SIN_SIN              0x18
+#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA          0x10
+#define MCF_GPIO_PAR_QSPI_SIN_GPIO             0x00
+#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK          0xFB
+#define MCF_GPIO_PAR_QSPI_SOUT_SOUT            0x04
+#define MCF_GPIO_PAR_QSPI_SOUT_GPIO            0x00
+#define MCF_GPIO_PAR_QSPI_SCK_UNMASK           0xFC
+#define MCF_GPIO_PAR_QSPI_SCK_SCK              0x03
+#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL          0x02
+#define MCF_GPIO_PAR_QSPI_SCK_GPIO             0x00
+
+/* Bit definitions and macros for PAR_TIMER for QSPI */
+#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK         0x3FFF
+#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2      0x4000
+#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK                0xFF3F
+#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3     0x0040
+
  #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x)       (((x)&0x03)<<6)
 
  #define MCF_SDRAMC_DCR                         0x000040
drivers/spi/Makefile +1 -0
index e5987e6..157e146 100644
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
  COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
  COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
  COBJS-$(CONFIG_CF_SPI) += cf_spi.o
+COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
  COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
  COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
  COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
drivers/spi/cf_qspi.c new file +257 -0

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