AMD Family 15h Performance Monitor Counters patches

Quoted 1 line

Quoted 1 line · Jacob Shin

# HG changeset patch
# User Jacob Shin <[email protected]>
# Date 1304524596 18000
# Node ID 349a9e537940f8bc340a2055cb5068b58809042f # Parent eeb1bb50ba13c36e44d4994e01d82d294f3c584a
xenoprof: Add support for AMD Family 15h processors

AMD Family 15h CPU mirrors legacy K7 performance monitor counters to a new location, and adds 2 new counters. This patch updates xenoprof to take advantage of the new counters.

Signed-off-by Jacob Shin <[email protected]>

diff -r eeb1bb50ba13 -r 349a9e537940 xen/arch/x86/oprofile/nmi_int.c

xen/arch/x86/oprofile/nmi_int.c +1 -1

@@ -30,7 +30,7 @@ struct op_counter_config counter_config[
 struct op_counter_config counter_config[OP_MAX_COUNTER];
 struct op_ibs_config ibs_config;
 
-static struct op_x86_model_spec const *__read_mostly model;
+struct op_x86_model_spec const *__read_mostly model;
 static struct op_msrs cpu_msrs[NR_CPUS];
 static unsigned long saved_lvtpc[NR_CPUS];
 

xen/arch/x86/oprofile/nmi_int.c +0 -0

                                 cpu_type = "x86-64/family15h";
                                 break;
 			}

diff -r eeb1bb50ba13 -r 349a9e537940 xen/arch/x86/oprofile/op_model_athlon.c

xen/arch/x86/oprofile/op_model_athlon.c +7 -2

@@ -24,8 +24,13 @@
 #include "op_x86_model.h"
 #include "op_counter.h"
 
-#define NUM_COUNTERS 4
-#define NUM_CONTROLS 4
+#define K7_NUM_COUNTERS 4
+#define K7_NUM_CONTROLS 4
+
+#define FAM15H_NUM_COUNTERS 6
+#define FAM15H_NUM_CONTROLS 6
+
+#define MAX_COUNTERS FAM15H_NUM_COUNTERS
 
 #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, 
 (msr_content));} while (0)

#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned
int)(l), -1);} while (0)

xen/arch/x86/oprofile/op_model_athlon.c +42 -10

@@ -44,9 +49,10 @@
 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 0x1ULL) << 41))
 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 0x1ULL) << 40))
 
-static unsigned long reset_value[NUM_COUNTERS];
+static unsigned long reset_value[MAX_COUNTERS];
 
 extern char svm_stgi_label[];
+extern struct op_x86_model_spec const *__read_mostly model;
 
 #ifdef CONFIG_X86_64
 u32 ibs_caps = 0;

@@ -175,26 +181,44 @@ static void athlon_fill_in_addresses(str
 	msrs->controls[3].addr = MSR_K7_EVNTSEL3;
 }
 
- 
+static void fam15h_fill_in_addresses(struct op_msrs * const msrs)
+{
+	msrs->counters[0].addr = MSR_FAM15H_PERFCTR0;
+	msrs->counters[1].addr = MSR_FAM15H_PERFCTR1;
+	msrs->counters[2].addr = MSR_FAM15H_PERFCTR2;
+	msrs->counters[3].addr = MSR_FAM15H_PERFCTR3;
+	msrs->counters[4].addr = MSR_FAM15H_PERFCTR4;
+	msrs->counters[5].addr = MSR_FAM15H_PERFCTR5;
+
+	msrs->controls[0].addr = MSR_FAM15H_EVNTSEL0;
+	msrs->controls[1].addr = MSR_FAM15H_EVNTSEL1;
+	msrs->controls[2].addr = MSR_FAM15H_EVNTSEL2;
+	msrs->controls[3].addr = MSR_FAM15H_EVNTSEL3;
+	msrs->controls[4].addr = MSR_FAM15H_EVNTSEL4;
+	msrs->controls[5].addr = MSR_FAM15H_EVNTSEL5;
+}
+
 static void athlon_setup_ctrs(struct op_msrs const * const msrs)
 {
 	uint64_t msr_content;
 	int i;
+	unsigned int const nr_ctrs = model->num_counters;
+	unsigned int const nr_ctrls = model->num_controls;
 
 	/* clear all counters */
-	for (i = 0 ; i < NUM_CONTROLS; ++i) {
+	for (i = 0 ; i < nr_ctrls; ++i) {
 		CTRL_READ(msr_content, msrs, i);
 		CTRL_CLEAR(msr_content);
 		CTRL_WRITE(msr_content, msrs, i);
 	}
 
 	/* avoid a false detection of ctr overflows in NMI handler */
-	for (i = 0; i < NUM_COUNTERS; ++i) {
+	for (i = 0; i < nr_ctrs; ++i) {
 		CTR_WRITE(1, msrs, i);
 	}
 
 	/* enable active counters */
-	for (i = 0; i < NUM_COUNTERS; ++i) {
+	for (i = 0; i < nr_ctrs; ++i) {
 		if (counter_config[i].enabled) {
 			reset_value[i] = counter_config[i].count;
 

@@ -300,6 +324,7 @@ static int athlon_check_ctrs(unsigned in
 	int mode = 0;
 	struct vcpu *v = current;
 	struct cpu_user_regs *guest_regs = guest_cpu_user_regs();
+	unsigned int const nr_ctrs = model->num_counters;
 
 	if (!guest_mode(regs) &&
 	    (regs->eip == (unsigned long)svm_stgi_label)) {

@@ -312,7 +337,7 @@ static int athlon_check_ctrs(unsigned in
 		mode = xenoprofile_get_mode(v, regs);
 	}
 
-	for (i = 0 ; i < NUM_COUNTERS; ++i) {
+	for (i = 0 ; i < nr_ctrs; ++i) {
 		CTR_READ(msr_content, msrs, i);
 		if (CTR_OVERFLOWED(msr_content)) {
 			xenoprof_log_event(current, regs, eip, mode, i);

@@ -373,7 +398,8 @@ static void athlon_start(struct op_msrs 
 {
 	uint64_t msr_content;
 	int i;
-	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
+	unsigned int const nr_ctrs = model->num_counters;
+	for (i = 0 ; i < nr_ctrs ; ++i) {
 		if (reset_value[i]) {
 			CTRL_READ(msr_content, msrs, i);
 			CTRL_SET_ACTIVE(msr_content);

@@ -401,10 +427,11 @@ static void athlon_stop(struct op_msrs c
 {
 	uint64_t msr_content;
 	int i;
+	unsigned int const nr_ctrs = model->num_counters;
 
 	/* Subtle: stop on all counters to avoid race with
 	 * setting our pm callback */
-	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
+	for (i = 0 ; i < nr_ctrs ; ++i) {
 		CTRL_READ(msr_content, msrs, i);
 		CTRL_SET_INACTIVE(msr_content);
 		CTRL_WRITE(msr_content, msrs, i);

@@ -512,11 +539,21 @@ void __init ibs_init(void)
 #endif /* CONFIG_X86_64 */
 
 struct op_x86_model_spec const op_athlon_spec = {
-	.num_counters = NUM_COUNTERS,
-	.num_controls = NUM_CONTROLS,
+	.num_counters = K7_NUM_COUNTERS,
+	.num_controls = K7_NUM_CONTROLS,
 	.fill_in_addresses = &athlon_fill_in_addresses,
 	.setup_ctrs = &athlon_setup_ctrs,
 	.check_ctrs = &athlon_check_ctrs,
 	.start = &athlon_start,
 	.stop = &athlon_stop
 };
+
+struct op_x86_model_spec const op_fam15h_spec = {
+	.num_counters = FAM15H_NUM_COUNTERS,
+	.num_controls = FAM15H_NUM_CONTROLS,
+	.fill_in_addresses = &fam15h_fill_in_addresses,
+	.setup_ctrs = &athlon_setup_ctrs,
+	.check_ctrs = &athlon_check_ctrs,
+	.start = &athlon_start,
+	.stop = &athlon_stop
+};

diff -r eeb1bb50ba13 -r 349a9e537940 xen/arch/x86/oprofile/op_x86_model.h

xen/arch/x86/oprofile/op_x86_model.h +1 -0

@@ -48,6 +48,7 @@ extern struct op_x86_model_spec const op
 extern struct op_x86_model_spec const op_p4_spec;
 extern struct op_x86_model_spec const op_p4_ht2_spec;
 extern struct op_x86_model_spec const op_athlon_spec;
+extern struct op_x86_model_spec const op_fam15h_spec;
 
 void arch_perfmon_setup_counters(void);
 #endif /* OP_X86_MODEL_H */

diff -r eeb1bb50ba13 -r 349a9e537940 xen/include/asm-x86/msr-index.h

xen/include/asm-x86/msr-index.h +13 -0

@@ -223,6 +223,19 @@
 #define MSR_K8_ENABLE_C1E		0xc0010055
 #define MSR_K8_VM_CR			0xc0010114
 #define MSR_K8_VM_HSAVE_PA		0xc0010117
+
+#define MSR_FAM15H_EVNTSEL0		0xc0010200
+#define MSR_FAM15H_PERFCTR0		0xc0010201
+#define MSR_FAM15H_EVNTSEL1		0xc0010202
+#define MSR_FAM15H_PERFCTR1		0xc0010203
+#define MSR_FAM15H_EVNTSEL2		0xc0010204
+#define MSR_FAM15H_PERFCTR2		0xc0010205
+#define MSR_FAM15H_EVNTSEL3		0xc0010206
+#define MSR_FAM15H_PERFCTR3		0xc0010207
+#define MSR_FAM15H_EVNTSEL4		0xc0010208
+#define MSR_FAM15H_PERFCTR4		0xc0010209
+#define MSR_FAM15H_EVNTSEL5		0xc001020a
+#define MSR_FAM15H_PERFCTR5		0xc001020b
 
 #define MSR_K8_FEATURE_MASK		0xc0011004
 #define MSR_K8_EXT_FEATURE_MASK		0xc0011005

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xen/arch/x86/hvm/vpmu.c void vpmu_initialise(struct vcpu *v) · line 107

Quoted 11 lines

Quoted 1 line

Quoted 1 line · Jacob Shin

xen/arch/x86/hvm/vpmu.c +1 -0

@@ -101,6 +101,7 @@ void vpmu_initialise(struct vcpu *v)
          switch ( family )
          {
          case 0x10:
+        case 0x15:
              vpmu->arch_vpmu_ops =&amd_vpmu_ops;
              break;
          default:

How about 0x11, 0x12, and 0x14?

Quoted 14 lines · Jan Beulich

xen/arch/x86/hvm/vpmu.c Wed May 04 19:17:59 2011 -0500 void vpmu_initialise(struct vcpu *v) · line 107

Quoted 11 lines

Quoted 1 line

Quoted 1 line · Jacob Shin

xen/arch/x86/hvm/vpmu.c Wed May 04 19:17:59 2011 -0500 renamed from xen/arch/x86/hvm/vpmu.c Wed May 04 10:56:36 2011 -0500 +1 -0

@@ -101,6 +101,7 @@ void vpmu_initialise(struct vcpu *v)
          switch ( family )
          {
          case 0x10:
+        case 0x15:
              vpmu->arch_vpmu_ops =&amd_vpmu_ops;
              break;
          default:

How about 0x11, 0x12, and 0x14?

Family 11h does not have guest only event monitoring .. but yes, we can enable 12h and 14h in the same path as the 10h. I'll send out a revised patchset later this afternoon.

Thanks!

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