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Fixes 16bit NAND support with the NDFC

PATCH New Alex Waterman 3 participants 6 messages May 19, 2011 – May 26, 2011

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#1 lore raw

PATCH 1/1 Fixes 16bit NAND support with the NDFC

Dear Alex Waterman,

Quoted 19 lines · In message <[email protected]> you wrote:

From ad2238044b9abc5a2094096219a1256a8ad091b0 Mon Sep 17 00:00:00 2001
From: Alex Waterman <[email protected]>
Date: Thu, 19 May 2011 15:08:36 -0400
Subject: [PATCH] [NAND] Fixes 16bit NAND support with the NDFC

This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added:

CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a
16 bit device is attached.
CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus
Controller configuration register.

Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian.

The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used.

Quoted 7 lines
Signed-off-by Alex Waterman <[email protected]>
Cc Scott Wood <[email protected]>
Cc Stefan Roese <[email protected]>
---
 drivers/mtd/nand/ndfc.c |   34 +++++++++++++++++++++++++++++-----
 nand_spl/nand_boot.c    |   11 ++++++++---
 2 files changed, 37 insertions(+), 8 deletions(-)

Please document the new CONFIG_SYS_* options in the README.

Best regards,

Wolfgang Denk

Signature · 5 lines
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author
#2 lore raw

PATCH 1/1 Fixes 16bit NAND support with the NDFC

From: Alex Waterman <[email protected]>
Date: Thu, 19 May 2011 15:08:36 -0400
Subject: [PATCH] [NAND] Fixes 16bit NAND support with the NDFC

This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added:

CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a
16 bit device is attached.
CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus
Controller configuration register.

Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian.

The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used.

Signed-off-by Alex Waterman <[email protected]>
Cc Scott Wood <[email protected]>
Cc Stefan Roese <[email protected]>
---
 README                  |    8 ++++++++
 drivers/mtd/nand/ndfc.c |   34 +++++++++++++++++++++++++++++-----
 nand_spl/nand_boot.c    |   11 ++++++++---
 3 files changed, 45 insertions(+), 8 deletions(-)

Here is the new patch with the README updated to reflect the config options added.

README +8 -0
index 6f3748d..3ede798 100644
@@ -2912,6 +2912,14 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_SRIOn_MEM_SIZE:
 		Size of SRIO port 'n' memory region
 
+- CONFIG_SYS_NDFC_16
+		Defined to tell the NDFC that the NAND chip is using a
+		16 bit bus.
+
+- CONFIG_SYS_NDFC_EBC0_CFG
+		Sets the EBC0_CFG register for the NDFC. If not defined
+		a default value will be used.
+
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs
drivers/mtd/nand/ndfc.c +29 -5
index 0729e0c..b533474 100644
@@ -37,6 +37,13 @@
 #include <asm/io.h>
 #include <asm/ppc4xx.h>
 
+#ifndef CONFIG_SYS_NAND_BCR
+#define CONFIG_SYS_NAND_BCR 0x80002222
+#endif
+#ifndef CONFIG_SYS_NDFC_EBC0_CFG
+#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
+#endif
+
 /*
  * We need to store the info, which chip-select (CS) is used for the
  * chip number. For example on Sequoia NAND chip #0 uses

@@ -140,11 +147,23 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 
 	return 0;
 }
-#endif /* #ifndef CONFIG_NAND_SPL */
 
-#ifndef CONFIG_SYS_NAND_BCR
-#define CONFIG_SYS_NAND_BCR 0x80002222
-#endif
+/*
+ * Read a byte from the NDFC.
+ */
+static uint8_t ndfc_read_byte(struct mtd_info *mtd)
+{
+
+	struct nand_chip *chip = mtd->priv;
+
+	if (chip->options & NAND_BUSWIDTH_16)
+		return (uint8_t) readw(chip->IO_ADDR_R);
+	else
+		return readb(chip->IO_ADDR_R);
+
+}
+
+#endif /* #ifndef CONFIG_NAND_SPL */
 
 void board_nand_select_device(struct nand_chip *nand, int chip)
 {

@@ -198,16 +217,21 @@ int board_nand_init(struct nand_chip *nand)
 	nand->ecc.bytes = 3;
 	nand->select_chip = ndfc_select_chip;
 
+#ifdef CONFIG_SYS_NDFC_16BIT
+	nand->options |= NAND_BUSWIDTH_16;
+#endif
+
 #ifndef CONFIG_NAND_SPL
 	nand->write_buf  = ndfc_write_buf;
 	nand->verify_buf = ndfc_verify_buf;
+	nand->read_byte = ndfc_read_byte;
 
 	chip++;
 #else
 	/*
 	 * Setup EBC (CS0 only right now)
 	 */
-	mtebc(EBC0_CFG, 0xb8400000);
+	mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
 
 	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
 	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
nand_spl/nand_boot.c +8 -3
index 9545a9a..4683c7c 100644
@@ -122,10 +122,15 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block)
 	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 
 	/*
-	 * Read one byte
+	 * Read one byte (or two if it's a 16 bit chip).
 	 */
-	if (readb(this->IO_ADDR_R) != 0xff)
-		return 1;
+	if (this->options & NAND_BUSWIDTH_16) {
+		if (readw(this->IO_ADDR_R) != 0xffff)
+			return 1;
+	} else {
+		if (readb(this->IO_ADDR_R) != 0xff)
+			return 1;
+	}
 
 	return 0;
 }
Signature · 8 lines
1.7.4.4


-- 
Alex Waterman
Computer Engineer
Phone: 215-896-4920
Email: awaterman at dawning.com
author
#3 lore raw

PATCH 1/1 Fixes 16bit NAND support with the NDFC

I know there has been a lot of activity related to other things in the U-Boot source, but has anyone had a chance to review this patch?

Regards,
Alex

Signature · 4 lines
Alex Waterman
Computer Engineer
Phone: 215-896-4920
Email: awaterman at dawning.com
#4 lore raw

PATCH 1/1 Fixes 16bit NAND support with the NDFC

Quoted 2 lines · On Thu, 26 May 2011 09:40:46 -0400 Alex Waterman <[email protected]> wrote:

I know there has been a lot of activity related to other things in the U-Boot source, but has anyone had a chance to review this patch?

Looks mostly OK to me -- I was going to consider it for next, rather than master, as despite "fix" in the name it's really adding new hardware support.

You may want to use an #ifdef for bus width in nand_boot.c rather than spending bytes to check it dynamically.

Likewise in the non-SPL driver code, you already have CONFIG_SYS_NDFC_16BIT, so why check dynamically in ndfc_read_byte()?

-Scott

author
#5 lore raw

PATCH 1/1 Fixes 16bit NAND support with the NDFC

Scott,

Quoted 2 lines

Looks mostly OK to me -- I was going to consider it for next, rather than master, as despite "fix" in the name it's really adding new hardware support.

Ahh, yeah, that makes sense. I will change "Fixes" to "Adds" for next submission.

Quoted 2 lines

You may want to use an #ifdef for bus width in nand_boot.c rather than spending bytes to check it dynamically.

OK. I suppose its unlikely that a NAND chip will swap from 8bit to 16bit (or vice versa) from one compile to another :).

Quoted 2 lines

Likewise in the non-SPL driver code, you already have CONFIG_SYS_NDFC_16BIT, so why check dynamically in ndfc_read_byte()?

My thought process was something along the lines of one compiled binary working on potentially multiple similar boards... Though in thinking about it, that seems like a needless requirement. I will change to #ifdefs for smaller code size. That's probably more useful overall.

Regards,
Alex

Signature · 4 lines
Alex Waterman
Computer Engineer
Phone: 215-896-4920
Email: awaterman at dawning.com