cpu model bug fixes and definition corrections: Correct archaic CPU model "model" field for Intel CPUs.

PATCH In review john cooper 1 participant 1 message May 23, 2011

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john cooper

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2011-05-23 22:09 UTC #0 lore raw

PATCH 1/7 cpu model bug fixes and definition corrections: Correct archaic CPU model "model" field for Intel CPUs.

Correct archaic CPU model "model" field for Intel CPUs. The old "model" values caused two known problems:

- Skype crashes on a winxp guest if model < 6, due to syscall vs. sysenter confusion.

- 32 bit windows doesn't enable MSI support if model < 13.

After consulting with Intel the following recommendations were received which more accurately represent shipped silicon.

Signed-off-by john cooper <[email protected]>

---

sysconfigs/target/target-x86_64.conf +3 -3

index 43ad282..0613870 100644
@@ -5,7 +5,7 @@
    level = "2"
    vendor = "GenuineIntel"
    family = "6"
-   model = "2"
+   model = "15"
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
    feature_ecx = "sse3 ssse3"

@@ -19,7 +19,7 @@
    level = "2"
    vendor = "GenuineIntel"
    family = "6"
-   model = "2"
+   model = "23"
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
    feature_ecx = "sse3 cx16 ssse3 sse4.1"

@@ -33,7 +33,7 @@
    level = "2"
    vendor = "GenuineIntel"
    family = "6"
-   model = "2"
+   model = "26"
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
    feature_ecx = "sse3 cx16 ssse3 sse4.1 sse4.2 popcnt"

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