cpu model bug fixes and definition corrections
PATCH 6/7 cpu model bug fixes and definition corrections
This patch adds Westmere as a qemu cpu model. The only additional guest visible feature of a Westmere relative to Nehalem is the inclusion of AES instructions. However as other non-ABI visible modifications exist along with fabrication changes, the CPUID data of the corresponding deployed silicon was altered slightly to reflect this.
We've seen isolated cases where apparently unrelated yet slightly incoherent CPUID data has caused problems, most notably during guest boot. Providing Westmere as a model separate fro Nehalem allows us to more easily address such quirks.
Signed-off-by john cooper <[email protected]>
---
sysconfigs/target/target-x86_64.conf +14 -0
@@ -43,6 +43,20 @@ model_id = "Intel Core i7 9xx (Nehalem Class Core i7)" [cpudef] + name = "Westmere" + level = "11" + vendor = "GenuineIntel" + family = "6" + model = "44" + stepping = "1" + feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36" + feature_ecx = "sse3 cx16 ssse3 sse4.1 sse4.2 x2apic popcnt aes" + extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu lm syscall nx" + extfeature_ecx = "lahf_lm" + xlevel = "0x8000000A" + model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)" + +[cpudef] name = "Opteron_G1" level = "5" vendor = "AuthenticAMD"
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