Skip to contentSkip to conversation

PEBS availability

DISCUSSION Pádraig Brady 3 participants 5 messages May 24, 2011 – May 27, 2011

lore
Share & tools
lore

Pádraig Brady

author
#0 lore raw

Hi,

I've just got a shiny new i3-2310M and am a
bit surprised that perf isn't listing
detailed stats like L1 cache misses etc.

$ perf stat true

Performance counter stats for 'true':

             1,239 cache-misses             #      1.555 M/sec
             9,314 cache-references         #     11.693 M/sec
             3,940 branch-misses            #      4.871 %
            80,885 branches                 #    101.546 M/sec
           403,808 instructions             #      0.000 IPC

<not counted> cycles
81 page-faults # 0.102 M/sec
0 CPU-migrations # 0.000 M/sec
1 context-switches # 0.001 M/sec
0.796537 task-clock-msecs # 0.032 CPUs

0.024654938 seconds time elapsed

I searched for a while but found it _very_ difficult to find info on what was available on particular intel CPUs.

I did see in the "Nehalem Core PMU programming guide":
http://software.intel.com/file/30320
that the above stats are core features and that the other counters I mentioned are PEBS (Precise Event Based Sampling) and are not available on all systems.

So am I out of look with my new i3 sandy bridge CPU? Are PEBS restricted to i7 versions only?
Is this documented anywhere?

Maybe I need some kernel support as hinted at by:
http://lwn.net/Articles/430100/
My kernel is 2.6.38.6-27.fc15.x86_64

cheers.
Pádraig.

#1 lore raw
Quoted 5 lines · Pádraig Brady

Hi,

I've just got a shiny new i3-2310M and am a
bit surprised that perf isn't listing
detailed stats like L1 cache misses etc.

'perf list | grep Hardware' will show you counters recognized by perf (perhaps with F15, "perf list hw" works). You can add more counters using the -e option.

You might also want to try 2.6.39 kernel and upstream version of perf. Ingo added a number of default counters to perf stat.

David

Quoted 41 lines
$ perf stat true

Performance counter stats for 'true':

             1,239 cache-misses             #      1.555 M/sec
             9,314 cache-references         #     11.693 M/sec
             3,940 branch-misses            #      4.871 %
            80,885 branches                 #    101.546 M/sec
           403,808 instructions             #      0.000 IPC

<not counted> cycles
81 page-faults # 0.102 M/sec
0 CPU-migrations # 0.000 M/sec
1 context-switches # 0.001 M/sec
0.796537 task-clock-msecs # 0.032 CPUs

0.024654938 seconds time elapsed

I searched for a while but found it _very_ difficult to find info on what was available on particular intel CPUs.

I did see in the "Nehalem Core PMU programming guide":
http://software.intel.com/file/30320
that the above stats are core features and that the other counters I mentioned are PEBS (Precise Event Based Sampling) and are not available on all systems.

So am I out of look with my new i3 sandy bridge CPU? Are PEBS restricted to i7 versions only?
Is this documented anywhere?

Maybe I need some kernel support as hinted at by:
http://lwn.net/Articles/430100/
My kernel is 2.6.38.6-27.fc15.x86_64

cheers.
Pádraig.
--
To unsubscribe from this list: send the line "unsubscribe linux-perf-users" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html

#2 lore raw
In reply to Pádraig Brady
Quoted 4 lines · Pádraig Brady

So am I out of look with my new i3 sandy bridge CPU? Are PEBS restricted to i7 versions only?
Is this documented anywhere?

i3 and i7 are marketing terms that don't mean much. Engineers care more about the output of:

#!/usr/bin/env python

import struct

def cpuid(eax):

    f = open("/dev/cpu/0/cpuid", "rb")
    f.seek(eax)
    data = f.read(16)
    f.close()
    return struct.unpack('IIII', data)

print "%x" % cpuid(1)[0]

Quoted 4 lines

Maybe I need some kernel support as hinted at by:
http://lwn.net/Articles/430100/
My kernel is 2.6.38.6-27.fc15.x86_64

Your kernel probably has support for most of PEBS. What's missing is support in user space for all the events in manuals.

http://thread.gmane.org/gmane.comp.linux.perfmon2.devel/2912

Kernel is still missing:

* Ability to dump all of x86 architectural state to perf.data on an event
* Uncore events
* Exposing offcore events to userspace

http://lwn.net/Articles/441209/ has a summary of recent discussions on this topic.

-Arun

author
#3 lore raw
Quoted 13 lines · Arun Sharma
Quoted 4 lines · Pádraig Brady

So am I out of look with my new i3 sandy bridge CPU? Are PEBS restricted to i7 versions only?
Is this documented anywhere?

i3 and i7 are marketing terms that don't mean much. Engineers care more about the output of:

#!/usr/bin/env python

import struct

Quoted 8 lines

def cpuid(eax):

    f = open("/dev/cpu/0/cpuid", "rb")
    f.seek(eax)
    data = f.read(16)
    f.close()
    return struct.unpack('IIII', data)

print "%x" % cpuid(1)[0]

206a7

Quoted 11 lines
Quoted 3 lines

Maybe I need some kernel support as hinted at by:
http://lwn.net/Articles/430100/
My kernel is 2.6.38.6-27.fc15.x86_64

Your kernel probably has support for most of PEBS. What's missing is support in user space for all the events in manuals.

http://thread.gmane.org/gmane.comp.linux.perfmon2.devel/2912

Kernel is still missing:

Quoted 7 lines

* Ability to dump all of x86 architectural state to perf.data on an event
* Uncore events
* Exposing offcore events to userspace

http://lwn.net/Articles/441209/ has a summary of recent discussions on this topic.

Excellent. I'll start digging from there.

cheers,
Pádraig.

author
#4 lore raw
In reply to Arun Sharma
Quoted 23 lines · Arun Sharma
Quoted 4 lines · Pádraig Brady

So am I out of look with my new i3 sandy bridge CPU? Are PEBS restricted to i7 versions only?
Is this documented anywhere?

i3 and i7 are marketing terms that don't mean much. Engineers care more about the output of:

#!/usr/bin/env python

import struct

def cpuid(eax):

    f = open("/dev/cpu/0/cpuid", "rb")
    f.seek(eax)
    data = f.read(16)
    f.close()
    return struct.unpack('IIII', data)

print "%x" % cpuid(1)[0]

Quoted 1 line
Quoted 8 lines
Quoted 3 lines

Maybe I need some kernel support as hinted at by:
http://lwn.net/Articles/430100/
My kernel is 2.6.38.6-27.fc15.x86_64

Your kernel probably has support for most of PEBS. What's missing is support in user space for all the events in manuals.

http://thread.gmane.org/gmane.comp.linux.perfmon2.devel/2912

Well that was easy.
My Fedora 15 kernel was missing support for sandy bridge PEBS, and creating a new bzImage with the patch I referenced makes the counters available:

old-kern:$ perf stat -e L1-dcache-loads true
Error: L1-dcache-loads event is not supported.
Fatal: Not all events could be opened.

new-kern:$ perf stat -e L1-dcache-loads true
98,331 L1-dcache-loads

cheers,
Pádraig.