Help on mem relocation issue when reworking on at91sam9rlek

Hi Reinhard,

I have an issue when I reworked U-Boot for AT91SAM9RL-EK. When I choose at91sam9rlek_nandflash', things are quite smooth. But when I choose at91sam9rlek_dataflash_cs0', uboot will stop booting after `relocate_code()'.

Do you have some hints about this? Thanks a lot.

Please see below the U-Boot output,

U-Boot 2011.06-rc1-02788-g2cca47e-dirty (Jun 09 2011 - 17:48:14)

U-Boot code: 21F00000 -> 21F2812C  BSS: -> 21F2A920
CPU: AT91SAM9RL
Crystal frequency:       12 MHz
CPU clock        :      200 MHz
Master clock     :      100 MHz
monitor len: 0002A920
ramsize: 04000000
TLB table at: 23ff0000
Top of RAM usable for U-Boot at: 23ff0000
LCD panel info: 240 x 320, 8 bit/pix

Reserving 76k for LCD Framebuffer at: 23fdd000
Reserving 170k for U-Boot at: 23fb2000
Reserving 180k for malloc() at: 23f85000
Reserving 24 Bytes for Board Info at: 23f84fe8
Reserving 144 Bytes for Global Data at: 23f84f58
New Stack Pointer is: 23f84f48
RAM Configuration:
Bank #0: 20000000 64 MiB
relocation Offset is: 020b2000
addr_sp: 23f84f48, id: 23f84f58, addr: 23fb2000

--- U-Boot will stop here ---

--- >8 --- my temporary work is below ----

index 76124e5..2bdc17b 100644
@@ -808,6 +808,7 @@ at91sam9263ek_config	:	unconfig
  	fi;
  	@$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel 

at91

+ifdef XXX
at91sam9rlek_nandflash_config \
at91sam9rlek_dataflash_config \
at91sam9rlek_dataflash_cs0_config \
@@ -819,6 +820,7 @@ at91sam9rlek_config : unconfig
echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
+endif

CPU9G20_128M_config \
CPU9G20_config \

b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c index 4f570f4..79ca59b 100644

@@ -23,10 +23,11 @@
   */
 
  #include <common.h>
+#include <asm/io.h>
  #include <asm/arch/at91_common.h>
  #include <asm/arch/at91_pmc.h>
  #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
 
  void at91_serial0_hw_init(void)
  {

@@ -34,7 +35,7 @@ void at91_serial0_hw_init(void)
 
  	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);		/* TXD0 */
  	at91_set_a_periph(AT91_PIO_PORTA, 7, 0);		/* RXD0 */
-	writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
+	writel(1 << ATMEL_ID_US0, &pmc->pcer);
  }
 
  void at91_serial1_hw_init(void)

@@ -43,7 +44,7 @@ void at91_serial1_hw_init(void)
 
  	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);		/* TXD1 */
  	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);		/* RXD1 */
-	writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
+	writel(1 << ATMEL_ID_US1, &pmc->pcer);
  }
 
  void at91_serial2_hw_init(void)

@@ -52,7 +53,7 @@ void at91_serial2_hw_init(void)
 
  	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);		/* TXD2 */
  	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);		/* RXD2 */
-	writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
+	writel(1 << ATMEL_ID_US2, &pmc->pcer);
  }
 
  void at91_serial3_hw_init(void)

@@ -61,7 +62,7 @@ void at91_serial3_hw_init(void)
 
  	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);		/* DRXD */
  	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  }
 
  void at91_serial_hw_init(void)

@@ -93,7 +94,7 @@ void at91_spi0_hw_init(unsigned long cs_mask)
  	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* SPI0_SPCK */
 
  	/* Enable clock */
-	writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI, &pmc->pcer);
 
  	if (cs_mask & (1 << 0)) {
  		at91_set_a_periph(AT91_PIO_PORTA, 28, 1);

b/arch/arm/include/asm/arch-at91/at91sam9rl.h
index 8eb0d4f..e36282e 100644

b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h index af8d914..35cde33 100644

@@ -14,83 +14,54 @@
  #ifndef AT91SAM9RL_MATRIX_H
  #define AT91SAM9RL_MATRIX_H
 
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration 

Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration
Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration
Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration
Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration
Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration
Register 5 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#ifndef __ASSEMBLY__

-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration
Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration
Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration
Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration
Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration
Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration
Register 5 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of
Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of
Default Master */
-#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * However, on the AT91SAM9260/9G20/9XE there exist only
+ * 6 Masters and 5 Slaves!
+ */
+struct at91_matrix {
+ u32 mcfg[16]; /* Master Configuration Registers */
+ u32 scfg[16]; /* Slave Configuration Registers */
+ u32 pras[16][2]; /* Priority Assignment Slave Registers */
+ u32 mrcr; /* Master Remap Control Register */
+ u32 filler[7];
+ u32 ebicsa; /* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */

-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A
for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A
for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A
for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A
for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A
for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A
for Slave 5 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)

-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control
Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0
(ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1
(ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)

-#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration
Register */
-#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled
memory block */
-#define AT91_MATRIX_ITCM_0 (0 << 0)
-#define AT91_MATRIX_ITCM_16 (5 << 0)
-#define AT91_MATRIX_ITCM_32 (6 << 0)
-#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled
memory block */
-#define AT91_MATRIX_DTCM_0 (0 << 4)
-#define AT91_MATRIX_DTCM_16 (5 << 4)
-#define AT91_MATRIX_DTCM_32 (6 << 4)
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20

-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select
Assignment Register */
-#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)

+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)

#endif

b/board/atmel/at91sam9rlek/at91sam9rlek.c
index e374917..9e5449a 100644

b/board/atmel/at91sam9rlek/config.mk
deleted file mode 100644
index e554a45..0000000

@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000

index 9634cc0..987e8c0 100644
@@ -26,12 +26,14 @@
  #include <asm/arch/at91sam9rl.h>
  #include <asm/arch/at91_pmc.h>
  #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 
  void coloured_LED_init(void)
  {
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
  	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+	writel(ATMEL_ID_PIOD, &pmc->pcer);
 
  	at91_set_gpio_output(CONFIG_RED_LED, 1);
  	at91_set_gpio_output(CONFIG_GREEN_LED, 1);

index ac20c81..561bafd 100644
@@ -83,6 +83,9 @@ at91sam9g20ek_dataflash_cs1  arm         arm926ejs 

at91sam9260ek atmel

  at91sam9xeek_nandflash       arm         arm926ejs   at91sam9260ek 
    atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
  at91sam9xeek_dataflash_cs0   arm         arm926ejs   at91sam9260ek 

atmel at91
at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek
atmel at91
at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1

+at91sam9rlek_nandflash       arm         arm926ejs   at91sam9rlek 
   atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
+at91sam9rlek_dataflash_cs0   arm         arm926ejs   at91sam9rlek 
   atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH_CS0
+at91sam9rlek_dataflash       arm         arm926ejs   at91sam9rlek 
   atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH_CS0
  snapper9260                  arm         arm926ejs   - 
    bluewater      at91        snapper9260:AT91SAM9260
  snapper9g20                  arm         arm926ejs   snapper9260 
    bluewater      at91        snapper9260:AT91SAM9G20
  cpu9260                      arm         arm926ejs   cpu9260 
    eukrea         at91        cpu9260:CPU9260