ATMEL (AT91): Fix compile errors for at91sam9m10g45 Eval Kit

index 4ad9b1f..08b961f 100644
@@ -26,42 +26,42 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* RXD0 */
-	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD1 */
-	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);		/* RXD2 */
-	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
 void at91_serial3_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
 }
 
 void at91_serial_hw_init(void)

@@ -86,14 +86,14 @@ void at91_serial_hw_init(void)
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI0_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);

@@ -123,14 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* SPI1_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* SPI1_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);

index 608af2c..0081ed7 100644
@@ -57,7 +57,7 @@ static unsigned long at91_css_to_rate(unsigned long css)
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
+		return AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:

index a087687..89a01ea 100644
@@ -134,3 +134,16 @@ ulong get_tbclk(void)
 {
 	return gd->timer_rate_hz;
 }
+
+/*
+ * Reset the timer.
+ */
+void reset_timer(void)
+{
+	/* TODO: write this code. */
+}
+
+void reset_timer_masked(void)
+{
+	/* TODO: write this code. */
+}

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146 lines not on this page · raw message

index ff59a2d..b939c5b 100644
@@ -23,15 +23,17 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/at91sam9g45.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
+#define AT91_PMC		ATMEL_BASE_PMC
 
 void coloured_LED_init(void)
 {
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+	writel(AT91_PMC_PCER, 1 << ATMEL_ID_PIODE);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);

index de74dcf..9c1b647 100644
@@ -28,17 +28,15 @@
 #define __CONFIG_H
 
 #define CONFIG_AT91_LEGACY
+#define CONFIG_ATMEL_LEGACY
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
+#define AT91_SLOW_CLOCK		32768
 #define CONFIG_SYS_HZ		1000
 
-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
-#ifdef CONFIG_AT91SAM9M10G45EK
-#define CONFIG_AT91SAM9M10G45	1	/* It's an Atmel AT91SAM9M10G45 SoC*/
-#else
-#define CONFIG_AT91SAM9G45	1	/* It's an Atmel AT91SAM9G45 SoC*/
-#endif
+#define CONFIG_AT91SAM9M10G45
+#define CONFIG_AT91FAMILY
 #define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 

@@ -48,6 +46,9 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
+#define ATMEL_PIO_PORTS		5 /* 5 PIO ports. */
+#define CONFIG_SYS_SDRAM_BASE   0x70000000
+
 /*
  * Hardware drivers
  */

@@ -57,6 +58,19 @@
 #undef CONFIG_USART1
 #undef CONFIG_USART2
 #define CONFIG_USART3		1	/* USART 3 is DBGU */
+#define CONFIG_USART_BASE	ATMEL_BASE_USART3
+#define CONFIG_USART_ID		3
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
 
 /* LCD */
 #define CONFIG_LCD			1

@@ -156,13 +170,13 @@
 #define CONFIG_USB_ATMEL
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_DOS_PARTITION		1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00700000	/* AT91SAM9G45_UHP_OHCI_BASE */
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00700000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9g45"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
 
-#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
 
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			0x23e00000

@@ -216,7 +230,8 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+				GENERATED_GBL_DATA_SIZE)
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
 #ifdef CONFIG_USE_IRQ