AM3505/3517 ZCN package support

PATCH Superseded Raphaël Assénat 2 participants 3 messages Jul 6, 2011

Subsystems (3)

Arm (32-bit) Arm sub-architectures OMAP2+ support

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Raphaël Assénat

author

2011-07-06 15:29 UTC #0 lore raw

PATCH 1/1 AM3505/3517 ZCN package support

This patch adds support for the AM35xx ZCN package specific muxmodes.

Signed-off-by Raphael Assenat <[email protected]>

arch/arm/mach-omap2/Kconfig +3 -0

index 4ae6257..5c880de 100644
@@ -103,6 +103,9 @@ config OMAP_PACKAGE_CBL
 config OMAP_PACKAGE_CBS
        bool
 
+config OMAP_PACKAGE_ZCN
+       bool
+
 comment "OMAP Board Type"
 	depends on ARCH_OMAP2PLUS

arch/arm/mach-omap2/mux.h +1 -0

index 2132308..f227503 100644
@@ -62,6 +62,7 @@
 
 /* Flags for omapX_mux_init */
 #define OMAP_PACKAGE_MASK		0xffff
+#define OMAP_PACKAGE_ZCN		9		/* 491-pin 0.65 */
 #define OMAP_PACKAGE_CBS		8		/* 547-pin 0.40 0.40 */
 #define OMAP_PACKAGE_CBL		7		/* 547-pin 0.40 0.40 */
 #define OMAP_PACKAGE_CBP		6		/* 515-pin 0.40 0.50 */

arch/arm/mach-omap2/mux34xx.c +535 ~~-45~~

604 lines not on this page · raw message

arch/arm/mach-omap2/mux34xx.h +37 -0

index 6543ebf..997387d 100644
@@ -316,6 +316,43 @@
 #define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET			0x232
 #define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET			0x234
 
+/* AM3505/3516 only */
+#define OMAP3_CONTROL_PADCONF_CCDC_PCLK_OFFSET			0x1b4
+#define OMAP3_CONTROL_PADCONF_CCDC_FIELD_OFFSET			0x1b6
+#define OMAP3_CONTROL_PADCONF_CCDC_HD_OFFSET			0x1b8
+#define OMAP3_CONTROL_PADCONF_CCDC_VD_OFFSET			0x1ba
+#define OMAP3_CONTROL_PADCONF_CCDC_WEN_OFFSET			0x1bc
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA0_OFFSET			0x1be
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA1_OFFSET			0x1c0
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA2_OFFSET			0x1c2
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA3_OFFSET			0x1c4
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA4_OFFSET			0x1c6
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA5_OFFSET			0x1c8
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA6_OFFSET			0x1ca
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA7_OFFSET			0x1cc
+#define OMAP3_CONTROL_PADCONF_RMII_MDIO_DATA_OFFSET		0x1ce
+#define OMAP3_CONTROL_PADCONF_RMII_MDIO_CLK_OFFSET		0x1d0
+#define OMAP3_CONTROL_PADCONF_RMII_RXD0_OFFSET			0x1d2
+#define OMAP3_CONTROL_PADCONF_RMII_RXD1_OFFSET			0x1d4
+#define OMAP3_CONTROL_PADCONF_RMII_CRS_DV_OFFSET		0x1d6
+#define OMAP3_CONTROL_PADCONF_RMII_RXER_OFFSET			0x1d8
+#define OMAP3_CONTROL_PADCONF_RMII_TXD0_OFFSET			0x1da
+#define OMAP3_CONTROL_PADCONF_RMII_TXD1_OFFSET			0x1dc
+#define OMAP3_CONTROL_PADCONF_RMII_TXEN_OFFSET			0x1de
+#define OMAP3_CONTROL_PADCONF_RMII_50MHZ_CLK_OFFSET		0x1e0
+#define OMAP3_CONTROL_PADCONF_USB0_DRVVBUS_OFFSET		0x1e2
+#define OMAP3_CONTROL_PADCONF_HECC1_TXD_OFFSET			0x1e4
+#define OMAP3_CONTROL_PADCONF_HECC1_RXD_OFFSET			0x1e6
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT7_OFFSET			0x1e8
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS0N_OFFSET			0x1ea
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS1N_OFFSET			0x1ec
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS2N_OFFSET			0x1ee
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS3N_OFFSET			0x1f0
+#define OMAP3_CONTROL_PADCONF_SDRC_STRBEN_DLY0_OFFSET		0x1f2
+#define OMAP3_CONTROL_PADCONF_SDRC_STRBEN_DLY1_OFFSET		0x1f4
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT8_OFFSET			0x1f6
+
+
 /* 36xx only */
 #define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET			0x236
 #define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET			0x570

Premi, Sanjeev

2011-07-06 16:12 UTC #1 lore raw

Quoted 11 lines

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Raphaël Assénat
Sent: Wednesday, July 06, 2011 8:59 PM
To: [email protected]
Subject: [PATCH] AM3505/3517 ZCN package support
This patch adds support for the AM35xx ZCN package specific muxmodes.
Signed-off-by Raphael Assenat <[email protected]>

[sp] Few quick comments below:

Quoted 48 lines

arch/arm/mach-omap2/Kconfig +3 -0

index 4ae6257..5c880de 100644
@@ -103,6 +103,9 @@ config OMAP_PACKAGE_CBL
 config OMAP_PACKAGE_CBS
        bool
 
+config OMAP_PACKAGE_ZCN
+       bool
+
 comment "OMAP Board Type"
 	depends on ARCH_OMAP2PLUS

arch/arm/mach-omap2/mux.h +1 -0

index 2132308..f227503 100644
@@ -62,6 +62,7 @@
 
 /* Flags for omapX_mux_init */
 #define OMAP_PACKAGE_MASK		0xffff
+#define OMAP_PACKAGE_ZCN		9		/*

491-pin 0.65 */
#define OMAP_PACKAGE_CBS 8 /*
547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBL 7 /*
547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBP 6 /*
515-pin 0.40 0.50 */

arch/arm/mach-omap2/mux34xx.c +3 -0

index 17f80e4..d42ac2e 100644
@@ -37,6 +37,9 @@
 	.balls		= { bb, bt },				
 	\
 }
 
+#define _OMAP3_NULL_MUXENTRY(M0) _OMAP3_MUXENTRY(M0, 0, 
 NULL, NULL,	\
+				NULL, NULL, NULL, NULL, NULL, NULL)
+
 /*

* Superset of all mux modes for omap3
*/

arch/arm/mach-omap2/mux34xx.c static struct omap_mux __initdata · line 657

Quoted 7 lines

arch/arm/mach-omap2/mux34xx.c +0 -3

@@ -651,51 +654,50 @@ static struct omap_mux __initdata 
 omap3_muxmodes[] = {
 		"gpio_166", NULL, NULL, "safe_mode"),
 
 	/* Only on 3630, see omap36xx_cbp_subset for the signals */
-	_OMAP3_MUXENTRY(GPMC_A11, 0,
-		NULL, NULL, NULL, NULL,
-		NULL, NULL, NULL, NULL),

[snip]...[snip]

arch/arm/mach-omap2/mux34xx.c static struct omap_mux __initdata omap3_muxmodes[] = { · line 659

Quoted 3 lines

arch/arm/mach-omap2/mux34xx.c +3 -0

+	_OMAP3_NULL_MUXENTRY(GPMC_A11),
+	_OMAP3_NULL_MUXENTRY(SAD2D_MBUSFLAG),
+	_OMAP3_NULL_MUXENTRY(SAD2D_MREAD),

[sp] These changes don't go with the current patch description.
You may want to keep them in a separate patch; and use here.

Quoted 19 lines

arch/arm/mach-omap2/mux34xx.c +19 -0

+
+	/* Only on AM35xx, see am35xx_zcn_subset for the signals */
+	_OMAP3_NULL_MUXENTRY(CCDC_PCLK),
+	_OMAP3_NULL_MUXENTRY(CCDC_FIELD),
+	_OMAP3_NULL_MUXENTRY(CCDC_HD),
+	_OMAP3_NULL_MUXENTRY(CCDC_VD),
+	_OMAP3_NULL_MUXENTRY(CCDC_WEN),
+	_OMAP3_NULL_MUXENTRY(CCDC_DATA0),
+	_OMAP3_NULL_MUXENTRY(CCDC_DATA1),
+	_OMAP3_NULL_MUXENTRY(CCDC_DATA2),
+	_OMAP3_NULL_MUXENTRY(CCDC_DATA3),
+	_OMAP3_NULL_MUXENTRY(CCDC_DATA4),
+	_OMAP3_NULL_MUXENTRY(CCDC_DATA5),
+	_OMAP3_NULL_MUXENTRY(CCDC_DATA6),
+	_OMAP3_NULL_MUXENTRY(CCDC_DATA7),
+	_OMAP3_NULL_MUXENTRY(RMII_MDIO_DATA),
+	_OMAP3_NULL_MUXENTRY(RMII_MDIO_CLK),
+	_OMAP3_NULL_MUXENTRY(RMII_RXD0),
+	_OMAP3_NULL_MUXENTRY(RMII_RXD1),

arch/arm/mach-omap2/mux34xx.c static struct omap_mux __initdata omap3_muxmodes[] = { · line 700

Quoted 10 lines

arch/arm/mach-omap2/mux34xx.c +10 -0

+	_OMAP3_NULL_MUXENTRY(RMII_CRS_DV),
+	_OMAP3_NULL_MUXENTRY(RMII_RXER),
+	_OMAP3_NULL_MUXENTRY(RMII_TXD0),
+	_OMAP3_NULL_MUXENTRY(RMII_TXD1),
+	_OMAP3_NULL_MUXENTRY(RMII_TXEN),
+	_OMAP3_NULL_MUXENTRY(RMII_50MHZ_CLK),
+	_OMAP3_NULL_MUXENTRY(USB0_DRVVBUS),
+	_OMAP3_NULL_MUXENTRY(HECC1_TXD),
+	_OMAP3_NULL_MUXENTRY(HECC1_RXD),
+

[sp] Extra line.

Quoted 12 lines

arch/arm/mach-omap2/mux34xx.c +2 -0

 	{ .reg_offset = OMAP_MUX_TERMINATOR },
 };

@@ -2026,6 +2028,490 @@ static struct omap_ball __initdata 
 omap36xx_cbp_ball[] = {
 #define omap36xx_cbp_ball	 NULL
 #endif
 
+/*
+ * Signals different on AM35XX ZCN package comapared to 34XX

CBC package
+ */

arch/arm/mach-omap2/mux34xx.c static struct omap_ball __initdata omap36xx_cbp_ball[] = { · line 2035

Quoted 2 lines

arch/arm/mach-omap2/mux34xx.c +2 -0

+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_ZCN)
+static struct omap_mux __initdata am35xx_zcn_subset[] = {

[snip]...[snip]

Quoted 12 lines

arch/arm/mach-omap2/mux34xx.c +11 -0

+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define am35xx_zcn_subset	NULL
+#endif
+
+/*
+ * Balls for AM35XX ZCN package
+ * 491-pin s-PBGA Package, 0.65mm Ball Pitch
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)

arch/arm/mach-omap2/mux34xx.c static struct omap_ball __initdata omap36xx_cbp_ball[] = { · line 2319

Quoted 2 lines

arch/arm/mach-omap2/mux34xx.c +2 -0

+		&& defined (CONFIG_OMAP_PACKAGE_ZCN)
+static struct omap_ball __initdata am35xx_zcn_ball[] = {

[snip]...[snip]

arch/arm/mach-omap2/mux34xx.c static struct omap_ball __initdata omap36xx_cbp_ball[] = { · line 2514

Quoted 8 lines

arch/arm/mach-omap2/mux34xx.c +8 -0

+
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define am35xx_zcn_ball	 NULL
+#endif
+
+

[sp] Extra line.

Quoted 23 lines

int __init omap3_mux_init(struct omap_board_mux
*board_subset, int flags)
{

arch/arm/mach-omap2/mux34xx.c +4 -0

 	struct omap_mux *package_subset;

@@ -2048,6 +2534,10 @@ int __init omap3_mux_init(struct 
 omap_board_mux *board_subset, int flags)
 		package_subset = omap36xx_cbp_subset;
 		package_balls = omap36xx_cbp_ball;
 		break;
+	case OMAP_PACKAGE_ZCN:
+		package_subset = am35xx_zcn_subset;
+		package_balls = am35xx_zcn_ball;
+		break;
 	default:
 		pr_err("%s Unknown omap package, mux

disabled\n", __func__);

arch/arm/mach-omap2/mux34xx.c +0 -0

 		return -EINVAL;

arch/arm/mach-omap2/mux34xx.h +0 -0

index 6543ebf..997387d 100644

arch/arm/mach-omap2/mux34xx.h line 321

Quoted 6 lines

arch/arm/mach-omap2/mux34xx.h +1 -0

@@ -316,6 +316,43 @@
 #define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET		
 	0x232
 #define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET		
 	0x234
 
+/* AM3505/3516 only */

[sp] Small typo in 3516.

Quoted 61 lines

arch/arm/mach-omap2/mux34xx.h +2 -0

+#define OMAP3_CONTROL_PADCONF_CCDC_PCLK_OFFSET		
 	0x1b4
+#define OMAP3_CONTROL_PADCONF_CCDC_FIELD_OFFSET

	0x1b6

arch/arm/mach-omap2/mux34xx.h +3 -0

+#define OMAP3_CONTROL_PADCONF_CCDC_HD_OFFSET			0x1b8
+#define OMAP3_CONTROL_PADCONF_CCDC_VD_OFFSET			0x1ba
+#define OMAP3_CONTROL_PADCONF_CCDC_WEN_OFFSET

	0x1bc
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA0_OFFSET		
	0x1be
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA1_OFFSET		
	0x1c0
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA2_OFFSET		
	0x1c2
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA3_OFFSET		
	0x1c4
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA4_OFFSET		
	0x1c6
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA5_OFFSET		
	0x1c8
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA6_OFFSET		
	0x1ca
+#define OMAP3_CONTROL_PADCONF_CCDC_DATA7_OFFSET		
	0x1cc

arch/arm/mach-omap2/mux34xx.h +3 -0

+#define OMAP3_CONTROL_PADCONF_RMII_MDIO_DATA_OFFSET		0x1ce
+#define OMAP3_CONTROL_PADCONF_RMII_MDIO_CLK_OFFSET		0x1d0
+#define OMAP3_CONTROL_PADCONF_RMII_RXD0_OFFSET

	0x1d2
+#define OMAP3_CONTROL_PADCONF_RMII_RXD1_OFFSET		
	0x1d4

arch/arm/mach-omap2/mux34xx.h +2 -0

+#define OMAP3_CONTROL_PADCONF_RMII_CRS_DV_OFFSET		0x1d6
+#define OMAP3_CONTROL_PADCONF_RMII_RXER_OFFSET

	0x1d8
+#define OMAP3_CONTROL_PADCONF_RMII_TXD0_OFFSET		
	0x1da
+#define OMAP3_CONTROL_PADCONF_RMII_TXD1_OFFSET		
	0x1dc
+#define OMAP3_CONTROL_PADCONF_RMII_TXEN_OFFSET		
	0x1de

arch/arm/mach-omap2/mux34xx.h +3 -0

+#define OMAP3_CONTROL_PADCONF_RMII_50MHZ_CLK_OFFSET		0x1e0
+#define OMAP3_CONTROL_PADCONF_USB0_DRVVBUS_OFFSET		0x1e2
+#define OMAP3_CONTROL_PADCONF_HECC1_TXD_OFFSET

	0x1e4
+#define OMAP3_CONTROL_PADCONF_HECC1_RXD_OFFSET		
	0x1e6
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT7_OFFSET		
	0x1e8
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS0N_OFFSET		
	0x1ea
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS1N_OFFSET		
	0x1ec
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS2N_OFFSET		
	0x1ee
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS3N_OFFSET		
	0x1f0
+#define OMAP3_CONTROL_PADCONF_SDRC_STRBEN_DLY0_OFFSET	
	0x1f2
+#define OMAP3_CONTROL_PADCONF_SDRC_STRBEN_DLY1_OFFSET	
	0x1f4
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT8_OFFSET		
	0x1f6

arch/arm/mach-omap2/mux34xx.h

Quoted 2 lines

arch/arm/mach-omap2/mux34xx.h +2 -0
+
+

[sp] Extra line.

Quoted 6 lines

/* 36xx only */

 #define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET		
	0x236
 #define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET		
	0x570

Quoted 6 lines

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Raphaël Assénat

author

2011-07-06 16:54 UTC #2 lore raw

Quoted 7 lines · Sanjeev

Quoted 7 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Raphaël Assénat
Sent: Wednesday, July 06, 2011 8:59 PM
To: [email protected]
Subject: [PATCH] AM3505/3517 ZCN package support

Quoted 6 lines

Quoted 4 lines
This patch adds support for the AM35xx ZCN package specific muxmodes.
Signed-off-by Raphael Assenat <[email protected]>
[sp] Few quick comments below:

Thank you for your comments. I just sent an updated version according to them.

Quoted 16 lines

Quoted 8 lines
+#define _OMAP3_NULL_MUXENTRY(M0) _OMAP3_MUXENTRY(M0, 0,
NULL, NULL, \
arch/arm/mach-omap2/mux34xx.c +2 -0
+				NULL, NULL, NULL, NULL, NULL, NULL)
+
 /*
  * Superset of all mux modes for omap3
  */
arch/arm/mach-omap2/mux34xx.c static struct omap_mux __initdata · line 657
Quoted 7 lines
arch/arm/mach-omap2/mux34xx.c +0 -3
@@ -651,51 +654,50 @@ static struct omap_mux __initdata 
 omap3_muxmodes[] = {
 		"gpio_166", NULL, NULL, "safe_mode"),
 
 	/* Only on 3630, see omap36xx_cbp_subset for the signals */
-	_OMAP3_MUXENTRY(GPMC_A11, 0,
-		NULL, NULL, NULL, NULL,
-		NULL, NULL, NULL, NULL),
[snip]...[snip]

Quoted 6 lines

arch/arm/mach-omap2/mux34xx.c static struct omap_mux __initdata omap3_muxmodes[] = { · line 659
Quoted 3 lines
arch/arm/mach-omap2/mux34xx.c +3 -0
+	_OMAP3_NULL_MUXENTRY(GPMC_A11),
+	_OMAP3_NULL_MUXENTRY(SAD2D_MBUSFLAG),
+	_OMAP3_NULL_MUXENTRY(SAD2D_MREAD),
[sp] These changes don't go with the current patch description.
You may want to keep them in a separate patch; and use here.

Ok, I will send another patch for this that will apply on top of the ZCN patch.

Regards,
Raphaël Assénat
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