x86: Resolving inconsistency with Intel processor manual
PATCH 1/1 x86: Resolving inconsistency with Intel processor manual
Following is from Notes of section 11.5.3 of Intel processor manual available at http://www.intel.com/Assets/PDF/manual/325384.pdf:
For the Pentium 4 and Intel Xeon processors, after the sequence of steps given above has been executed, the cache lines containing the code between the end of the WBINVD instruction and before the MTRRS have actually been disabled may be retained in the cache hierarchy. Here, to remove code from the cache completely, a second WBINVD instruction must be executed after the MTRRs have been disabled.
This patch provides resolution for that.
Ideally, I will like to make changes only for Pentium 4 and Xeon processors. But, I am not finding easier way to do it.
And, extra wbinvd() instruction does not hurt much for other processors.
--- arch/x86/kernel/cpu/mtrr/generic.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/x86/kernel/cpu/mtrr/generic.c +1 -0
@@ -693,6 +693,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)/* Disable MTRRs, and set the default type to uncached */ mtrr_wrmsr (MSR_MTRRdefType, deftype_lo & ~0xcff , deftype_hi); +wbinvd (); } static void post_set(void) __releases(set_atomicity_lock)
Signature · 1 line
1.7.5.1
[tip:x86/urgent] x86/mtrr: Resolve inconsistency with Intel processor manual
Commit-ID: 8dbf4a30033ff61091015f0076e872b5c8f717cc Gitweb: http://git.kernel.org/tip/8dbf4a30033ff61091015f0076e872b5c8f717cc Author: Ajaykumar Hotchandani <[email protected]> AuthorDate: Fri, 11 Nov 2011 18:31:57 +0530 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 5 Dec 2011 15:06:15 +0100
x86/mtrr: Resolve inconsistency with Intel processor manual
Following is from Notes of section 11.5.3 of Intel processor manual available at:
http://www.intel.com/Assets/PDF/manual/325384.pdf
For the Pentium 4 and Intel Xeon processors, after the sequence of steps given above has been executed, the cache lines containing the code between the end of the WBINVD instruction and before the MTRRS have actually been disabled may be retained in the cache hierarchy. Here, to remove code from the cache completely, a second WBINVD instruction must be executed after the MTRRs have been disabled.
This patch provides resolution for that.
Ideally, I will like to make changes only for Pentium 4 and Xeon processors. But, I am not finding easier way to do it. And, extra wbinvd() instruction does not hurt much for other processors.
--- arch/x86/kernel/cpu/mtrr/generic.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/x86/kernel/cpu/mtrr/generic.c +1 -0
@@ -694,6 +694,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)/* Disable MTRRs, and set the default type to uncached */ mtrr_wrmsr (MSR_MTRRdefType, deftype_lo & ~0xcff , deftype_hi); +wbinvd (); } static void post_set(void) __releases(set_atomicity_lock)