MX28 fec clock frequency
Hi all,
I'm trying to get the fec clock frequency on the i.MX28 processor. I0 need it for a PTP clock and it seems that I get a wrong value:clk_get_rate returns 151578947.
I've tried to get all the clock rates up to the crystal clock through the parent field and got these results:
CLKRATE: 151578947
CLKRATE: 151578947
CLKRATE: 454736842
CLKRATE: 454736842
CLKRATE: 480000000
CLKRATE: 24000000
The first one is the fec_enet_private's clock and then the parents. Are these correct values?
I'm currently using the master branch from git.pengutronix.de/git/imx
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Rusk? P?ter Fejleszt?m?rn?k Prolan Zrt. / Prolan Co. Hungary 2011 Budakal?sz, Szentendrei ?t 1-3. Tel./Phone: +36 20 954 3118 Fax: +36 26 540 420 E-mail: rusko.peter at prolan.hu Web: www.prolan.hu Timezone:CET
Hi Peter,
Quoted 6 lines · Peter Rusko
Hi all,
I'm trying to get the fec clock frequency on the i.MX28 processor. I0 need it for a PTP clock and it seems that I get a wrong value:
clk_get_ratereturns 151578947.
The ptp clock (CLK_ENET_TIME) was missed from the initial imx28 clock support. The fec_clk which is one child of hbus_clk (151 MHz) is taken as MDIO clock in fec driver.
Signature · 2 lines
Regards, Shawn
Quoted 5 lines · Shawn Guo
Hi Peter,
Quoted 2 lines · Peter Rusko
Hi all,
Quoted 9 lines
Quoted 4 lines
I'm trying to get the fec clock frequency on the i.MX28 processor. I0 need it for a PTP clock and it seems that I get a wrong value:
clk_get_ratereturns 151578947.The ptp clock (
CLK_ENET_TIME) was missed from the initial imx28 clock support. Thefec_clkwhich is one child ofhbus_clk(151 MHz) is taken as MDIO clock in fec driver.
I'm working on a ptp driver now and I can't deal with the clock.
I've added the CLK_ENET_TIME clock and set it to 40MHz. It should give a 25ns period for the counter in ptp. However the ptp clock is too slow.
If i increase the number (up to the maximum, which is 0x7f), the clock is still slower then normal. It's like the CLK_ENET_TIME frequency is less then I think. What can be the problem?
I've attached a patch.
Regards,
Signature · 17 lines
Rusk? P?ter Fejleszt?m?rn?k Prolan Zrt. / Prolan Co. Hungary 2011 Budakal?sz, Szentendrei ?t 1-3. Tel./Phone: +36 20 954 3118 Fax: +36 26 540 420 E-mail: rusko.peter at prolan.hu Web: www.prolan.hu Timezone:CET -------------- next part -------------- A non-text attachment was scrubbed... Name: fec_ptp.patch Type: text/x-patch Size: 19053 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20120109/09c41f10/attachment-0001.bin>
Review
Quoted 5 lines · Peter Rusko
(quoted diff) +5
-0+ /* ENET_CLK setup */ + enet_clk.set_parent(&enet_clk, &pll0_clk); + __raw_writel(BF_CLKCTRL_ENET_DIV(12), + CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); +
I'm not sure it's causing the problem you are seeing. But from i.MX28 spec, it seems that bit BUSY_TIME of register HW_CLKCTRL_ENET should be polled for new divider setting?
Signature · 2 lines
Regards, Shawn
Quoted 4 lines
I'm not sure it's causing the problem you are seeing. But from i.MX28 spec, it seems that bit
BUSY_TIMEof registerHW_CLKCTRL_ENETshould be polled for new divider setting?
Thank you, I've added the check, but unfortunately it didn't help :(
Signature · 10 lines
Rusk? P?ter Fejleszt?m?rn?k Prolan Zrt. / Prolan Co. Hungary 2011 Budakal?sz, Szentendrei ?t 1-3. Tel./Phone: +36 20 954 3118 Fax: +36 26 540 420 E-mail: rusko.peter at prolan.hu Web: www.prolan.hu Timezone:CET
Quoted 7 lines · Peter Rusko
Quoted 4 lines
I'm not sure it's causing the problem you are seeing. But from i.MX28 spec, it seems that bit
BUSY_TIMEof registerHW_CLKCTRL_ENETshould be polled for new divider setting?Thank you, I've added the check, but unfortunately it didn't help :(
Another point worth checking is bit field ATIME_INC of register HW_ENET_MAC_ATIME_INC. It should be 25 if your CLK_ENET_TIME runs at 40 MHz.
Signature · 2 lines
Regards, Shawn
Quoted 4 lines · Shawn Guo
Another point worth checking is bit field
ATIME_INCof registerHW_ENET_MAC_ATIME_INC. It should be 25 if yourCLK_ENET_TIMEruns at 40 MHz.
No, that was set correctly. Finally, I've found my mistake. I've overwritten the other bits when writing the divider so xtal clock was selected automatically.
Silly little mistake, isn't it? :) Anyway, thank you for your help.
Signature · 10 lines
Rusk? P?ter Fejleszt?m?rn?k Prolan Zrt. / Prolan Co. Hungary 2011 Budakal?sz, Szentendrei ?t 1-3. Tel./Phone: +36 20 954 3118 Fax: +36 26 540 420 E-mail: rusko.peter at prolan.hu Web: www.prolan.hu Timezone:CET