mx28: fix SPL code to make USB booting work

PATCH New Matthias Fuchs 3 participants 4 messages Feb 7, 2012 Arm (32-bit)

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Matthias Fuchs

author

2012-02-07 09:32 UTC #0 lore raw

PATCH v3 1/1 mx28: fix SPL code to make USB booting work

This patch fixes booting i.MX28 CPUs via USB download. In this mode the CPU's bootrom implements a USB HID device that accepts a bootstream.

When downloading the bootstream via USB, first the SPL code is received and executed. Then the u-boot image is received and called.

The USB bootmode is interrupt driven.

This patch fixes two things:

1) The ARM's fast interrupt mode is disabled when the SPL code has been run. So save and restore the CPSR register.

2) Save and restore c1 control register: the exception vector location needs to be set back to bootrom space to make the USB interrupts work again. The SPL code needs to change this option for the ram size probing.

Signed-off-by Matthias Fuchs <[email protected]>

---
changes in v2:
- store old SPSR on stack instead of jiggling around with some bits
- remove #ifndef CONFIG_SKIP_LOWLEVEL_INIT
changes in v3:
- also store C1 register on stack

 arch/arm/cpu/arm926ejs/mx28/start.S |   21 ++++++++++++++++++++-
 1 files changed, 20 insertions(+), 1 deletions(-)

arch/arm/cpu/arm926ejs/mx28/start.S +20 -1

index 2cd4d73..e572b78 100644
@@ -167,10 +167,15 @@ _reset:
 	 */
 	push	{r0-r12,r14}
 
+	/* save control register c1 */
+	mrc	p15, 0, r0, c1, c0, 0
+	push	{r0}
+
 	/*
-	 * set the cpu to SVC32 mode
+	 * set the cpu to SVC32 mode and store old CPSR register content
 	 */
 	mrs	r0,cpsr
+	push	{r0}
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0

@@ -185,6 +190,20 @@ _reset:
 
 	bl	board_init_ll
 
+	/*
+	 * restore bootrom's cpu mode (especially FIQ)
+	 */
+	pop	{r0}
+	msr	cpsr,r0
+
+	/*
+	 * restore c1 register
+	 * (especially set exception vector location back to
+	 * bootrom space which is required by bootrom for USB boot)
+	 */
+	pop	{r0}
+	mcr	p15, 0, r0, c1, c0, 0
+
 	pop	{r0-r12,r14}
 	bx	lr

Signature · 1 line

1.6.1

Marek Vasut

2012-02-07 16:54 UTC #1 lore raw

PATCH v3 1/1 mx28: fix SPL code to make USB booting work

Quoted 62 lines

This patch fixes booting i.MX28 CPUs via USB download. In this mode the CPU's bootrom implements a USB HID device that accepts a bootstream.
When downloading the bootstream via USB, first the SPL code is received and executed. Then the u-boot image is received and called.
The USB bootmode is interrupt driven.
This patch fixes two things:
1) The ARM's fast interrupt mode is disabled when the SPL code has been run. So save and restore the CPSR register.
2) Save and restore c1 control register: the exception vector location needs to be set back to bootrom space to make the USB interrupts work again. The SPL code needs to change this option for the ram size probing.
Signed-off-by Matthias Fuchs <[email protected]>
---
changes in v2:
- store old SPSR on stack instead of jiggling around with some bits
- remove #ifndef CONFIG_SKIP_LOWLEVEL_INIT
changes in v3:
- also store C1 register on stack
 arch/arm/cpu/arm926ejs/mx28/start.S |   21 ++++++++++++++++++++-
 1 files changed, 20 insertions(+), 1 deletions(-)
(quoted diff) +0 -0
b/arch/arm/cpu/arm926ejs/mx28/start.S index 2cd4d73..e572b78 100644
arch/arm/cpu/arm926ejs/mx28/start.S +12 -1
@@ -167,10 +167,15 @@ _reset:
 	 */
 	push	{r0-r12,r14}
 
+	/* save control register c1 */
+	mrc	p15, 0, r0, c1, c0, 0
+	push	{r0}
+
 	/*
-	 * set the cpu to SVC32 mode
+	 * set the cpu to SVC32 mode and store old CPSR register content
 	 */
 	mrs	r0,cpsr
+	push	{r0}
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
@@ -185,6 +190,20 @@ _reset:
 
 	bl	board_init_ll
 
+	/*
+	 * restore bootrom's cpu mode (especially FIQ)
+	 */
+	pop	{r0}
+	msr	cpsr,r0
+

arch/arm/cpu/arm926ejs/mx28/start.S _reset: · line 208

Quoted 10 lines

arch/arm/cpu/arm926ejs/mx28/start.S +8 -0

+	/*
+	 * restore c1 register
+	 * (especially set exception vector location back to
+	 * bootrom space which is required by bootrom for USB boot)
+	 */
+	pop	{r0}
+	mcr	p15, 0, r0, c1, c0, 0
+
 	pop	{r0-r12,r14}
 	bx	lr

Yep, looks fine. Stefano, can you apply? Or shall I start hand-picking these mx28 patches and then send you a pullrq?

Acked-by Marek Vasut <[email protected]>

Stefano Babic

2012-02-07 16:56 UTC #2 lore raw

PATCH v3 1/1 mx28: fix SPL code to make USB booting work

Quoted 67 lines · Marek Vasut

Quoted 67 lines
This patch fixes booting i.MX28 CPUs via USB download. In this mode the CPU's bootrom implements a USB HID device that accepts a bootstream.
When downloading the bootstream via USB, first the SPL code is received and executed. Then the u-boot image is received and called.
The USB bootmode is interrupt driven.
This patch fixes two things:
1) The ARM's fast interrupt mode is disabled when the SPL code has been run. So save and restore the CPSR register.
2) Save and restore c1 control register: the exception vector location needs to be set back to bootrom space to make the USB interrupts work again. The SPL code needs to change this option for the ram size probing.
Signed-off-by Matthias Fuchs <[email protected]>
---
changes in v2:
- store old SPSR on stack instead of jiggling around with some bits
- remove #ifndef CONFIG_SKIP_LOWLEVEL_INIT
changes in v3:
- also store C1 register on stack
 arch/arm/cpu/arm926ejs/mx28/start.S |   21 ++++++++++++++++++++-
 1 files changed, 20 insertions(+), 1 deletions(-)
(quoted diff) +0 -0
b/arch/arm/cpu/arm926ejs/mx28/start.S index 2cd4d73..e572b78 100644
arch/arm/cpu/arm926ejs/mx28/start.S +17 -1
@@ -167,10 +167,15 @@ _reset:
 	 */
 	push	{r0-r12,r14}
 
+	/* save control register c1 */
+	mrc	p15, 0, r0, c1, c0, 0
+	push	{r0}
+
 	/*
-	 * set the cpu to SVC32 mode
+	 * set the cpu to SVC32 mode and store old CPSR register content
 	 */
 	mrs	r0,cpsr
+	push	{r0}
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
@@ -185,6 +190,20 @@ _reset:
 
 	bl	board_init_ll
 
+	/*
+	 * restore bootrom's cpu mode (especially FIQ)
+	 */
+	pop	{r0}
+	msr	cpsr,r0
+
+	/*
+	 * restore c1 register
+	 * (especially set exception vector location back to
+	 * bootrom space which is required by bootrom for USB boot)
+	 */

Quoted 8 lines

arch/arm/cpu/arm926ejs/mx28/start.S _reset: · line 208
Quoted 5 lines
arch/arm/cpu/arm926ejs/mx28/start.S +3 -0
+	pop	{r0}
+	mcr	p15, 0, r0, c1, c0, 0
+
 	pop	{r0-r12,r14}
 	bx	lr
Yep, looks fine. Stefano, can you apply? Or shall I start hand-picking these mx28 patches and then send you a pullrq?

No problem, I will apply it to u-boot-imx

Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Stefano Babic

2012-02-07 17:06 UTC #3 lore raw

PATCH v3 1/1 mx28: fix SPL code to make USB booting work

In reply to Matthias Fuchs

Quoted 15 lines · Matthias Fuchs

This patch fixes booting i.MX28 CPUs via USB download. In this mode the CPU's bootrom implements a USB HID device that accepts a bootstream.
When downloading the bootstream via USB, first the SPL code is received and executed. Then the u-boot image is received and called.
The USB bootmode is interrupt driven.
This patch fixes two things:
1) The ARM's fast interrupt mode is disabled when the SPL code has been run. So save and restore the CPSR register.

Quoted 6 lines

2) Save and restore c1 control register: the exception vector location needs to be set back to bootrom space to make the USB interrupts work again. The SPL code needs to change this option for the ram size probing.
Signed-off-by Matthias Fuchs <[email protected]>

Applied to u-boot-imx, thanks

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================