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ARM: EXYNOS: add exynos lcd clock interface

PATCH Superseded Donghwa Lee 2 participants 2 messages Apr 2, 2012

Subsystems (2)
Arm (32-bit) Arm Samsung Exynos

v2 of 3 Superseded Latest is v3 →

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Donghwa Lee

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#0 lore raw

PATCH v2 3/4 ARM: EXYNOS: add exynos lcd clock interface

To get lcd clock in EXYNOS display driver, added get_lcd_clk() interface.

Signed-off-by Donghwa Lee <[email protected]>
Signed-off-by Inki Dae <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 arch/arm/cpu/armv7/exynos/clock.c |   72 +++++++++++++++++++++++++++++++++++++
 1 files changed, 72 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +72 -0
index 2f7048b..b13fba3 100644
@@ -414,6 +414,66 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 	writel(val, addr);
 }
 
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos4_get_lcd_clk(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL [3:0]
+	 */
+	sel = readl(&clk->src_lcd0);
+	sel = sel & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_lcd0);
+	ratio = ratio & 0xf;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
+static unsigned long exynos4_set_lcd_clk(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+	unsigned int cfg = 0;
+
+	/* set lcd src clock */
+	cfg = readl(&clk->src_lcd0);
+	cfg &= ~(0xf);
+	cfg |= 0x6;
+	writel(cfg, &clk->src_lcd0);
+
+	cfg = readl(&clk->gate_ip_lcd0);
+	cfg |= 1 << 0;
+	writel(cfg, &clk->gate_ip_lcd0);
+
+	/* set fimd ratio */
+	cfg &= ~(0xf);
+	cfg |= 0x1;
+	writel(cfg, &clk->div_lcd0);
+
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5())

@@ -453,3 +513,15 @@ void set_mmc_clk(int dev_index, unsigned int div)
 	else
 		exynos4_set_mmc_clk(dev_index, div);
 }
+
+unsigned long get_lcd_clk(void)
+{
+	if (cpu_is_exynos4())
+		return exynos4_get_lcd_clk();
+}
+
+unsigned long set_lcd_clk(void)
+{
+	if (cpu_is_exynos4())
+		return exynos4_set_lcd_clk();
+}
Signature · 1 line
1.7.4.1
#1 lore raw

PATCH v2 3/4 ARM: EXYNOS: add exynos lcd clock interface

Quoted 54 lines · Donghwa Lee

To get lcd clock in EXYNOS display driver, added get_lcd_clk() interface.

Signed-off-by Donghwa Lee <[email protected]>
Signed-off-by Inki Dae <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>

---
?arch/arm/cpu/armv7/exynos/clock.c | ? 72 +++++++++++++++++++++++++++++++++++++ ?1 files changed, 72 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +37 -0
index 2f7048b..b13fba3 100644
@@ -414,6 +414,66 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 ? ? ? ?writel(val, addr);
 ?}
 
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos4_get_lcd_clk(void)
+{
+ ? ? ? struct exynos4_clock *clk =
+ ? ? ? ? ? ? ? (struct exynos4_clock *)samsung_get_base_clock();
+ ? ? ? unsigned long pclk, sclk;
+ ? ? ? unsigned int sel;
+ ? ? ? unsigned int ratio;
+
+ ? ? ? /*
+ ? ? ? ?* CLK_SRC_LCD0
+ ? ? ? ?* FIMD0_SEL [3:0]
+ ? ? ? ?*/
+ ? ? ? sel = readl(&clk->src_lcd0);
+ ? ? ? sel = sel & 0xf;
+
+ ? ? ? if (sel == 0x6)
+ ? ? ? ? ? ? ? sclk = get_pll_clk(MPLL);
+ ? ? ? else if (sel == 0x7)
+ ? ? ? ? ? ? ? sclk = get_pll_clk(EPLL);
+ ? ? ? else if (sel == 0x8)
+ ? ? ? ? ? ? ? sclk = get_pll_clk(VPLL);
+ ? ? ? else
+ ? ? ? ? ? ? ? return 0;
+
+ ? ? ? /*
+ ? ? ? ?* CLK_DIV_LCD0
+ ? ? ? ?* FIMD0_RATIO [3:0]
+ ? ? ? ?*/
+ ? ? ? ratio = readl(&clk->div_lcd0);
+ ? ? ? ratio = ratio & 0xf;
+
+ ? ? ? pclk = sclk / (ratio + 1);
+
+ ? ? ? return pclk;
+}
+

arch/arm/cpu/armv7/exynos/clock.c static void exynos5_set_mmc_clk(int dev_index, unsigned int div) · line 463

Quoted 10 lines
arch/arm/cpu/armv7/exynos/clock.c +10 -0
+static unsigned long exynos4_set_lcd_clk(void)
+{
+ ? ? ? struct exynos4_clock *clk =
+ ? ? ? ? ? (struct exynos4_clock *)samsung_get_base_clock();
+ ? ? ? unsigned int cfg = 0;
+
+ ? ? ? /* set lcd src clock */
+ ? ? ? cfg = readl(&clk->src_lcd0);
+ ? ? ? cfg &= ~(0xf);
+ ? ? ? cfg |= 0x6;

what is 0x6?

arch/arm/cpu/armv7/exynos/clock.c static void exynos5_set_mmc_clk(int dev_index, unsigned int div) · line 472

Quoted 9 lines
arch/arm/cpu/armv7/exynos/clock.c +9 -0
+ ? ? ? writel(cfg, &clk->src_lcd0);
+
+ ? ? ? cfg = readl(&clk->gate_ip_lcd0);
+ ? ? ? cfg |= 1 << 0;
+ ? ? ? writel(cfg, &clk->gate_ip_lcd0);
+
+ ? ? ? /* set fimd ratio */
+ ? ? ? cfg &= ~(0xf);
+ ? ? ? cfg |= 0x1;

what is 0x1?

Quoted 11 lines
arch/arm/cpu/armv7/exynos/clock.c +4 -0
+ ? ? ? writel(cfg, &clk->div_lcd0);
+
+}
+
 ?unsigned long get_pll_clk(int pllreg)
 ?{
 ? ? ? ?if (cpu_is_exynos5())

@@ -453,3 +513,15 @@ void set_mmc_clk(int dev_index, unsigned int div)

? ? ? ?else
? ? ? ? ? ? ? ?exynos4_set_mmc_clk(dev_index, div); ?}

arch/arm/cpu/armv7/exynos/clock.c void set_mmc_clk(int dev_index, unsigned int div)

Quoted 5 lines
arch/arm/cpu/armv7/exynos/clock.c +5 -0
+
+unsigned long get_lcd_clk(void)
+{
+ ? ? ? if (cpu_is_exynos4())
+ ? ? ? ? ? ? ? return exynos4_get_lcd_clk();

need return.

arch/arm/cpu/armv7/exynos/clock.c void set_mmc_clk(int dev_index, unsigned int div) · line 523

Quoted 3 lines
arch/arm/cpu/armv7/exynos/clock.c +3 -0
+}
+
+unsigned long set_lcd_clk(void)

This function should be void function.

arch/arm/cpu/armv7/exynos/clock.c

Quoted 5 lines
arch/arm/cpu/armv7/exynos/clock.c +4 -1
+{
+ ? ? ? if (cpu_is_exynos4())
+ ? ? ? ? ? ? ? return exynos4_set_lcd_clk();
+}
--

Thanks,
Minkyu Kang.

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