perf_events: update PEBS event constraints (v2)

PATCH In review Stephane Eranian 3 participants 5 messages Mar 1, 2011 – Mar 4, 2011

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x86 perf events

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Stephane Eranian

author

2011-03-01 21:22 UTC #0 lore raw

PATCH 1/1 perf_events: update PEBS event constraints (v2)

This patch updates PEBS event constraints for Intel Atom, Nehalem, Westmere.

This patch also reorganizes the PEBS format/constraint detection code. It is now based on processor model and not PEBS format. Two processors may use the same PEBS format without have the same list of PEBS events.

In this second version, we simplified the initialization of the PEBS constraints by leveraging the existing switch() statement in perf_event_intel.c. We also renamed the constraint tables to be more consistent with regular constraints.

Signed-off-by Stephane Eranian <[email protected]>

---

arch/x86/kernel/cpu/perf_event_intel.c +5 -0

index 084b383..ddf6c4f 100644
@@ -1024,6 +1024,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_core();
 
 		x86_pmu.event_constraints = intel_core2_event_constraints;
+		x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
 		pr_cont("Core2 events, ");
 		break;

@@ -1036,6 +1037,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_nhm();
 
 		x86_pmu.event_constraints = intel_nehalem_event_constraints;
+		x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
 		x86_pmu.enable_all = intel_pmu_nhm_enable_all;
 		pr_cont("Nehalem events, ");
 		break;

@@ -1047,6 +1049,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_atom();
 
 		x86_pmu.event_constraints = intel_gen_event_constraints;
+		x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
 		pr_cont("Atom events, ");
 		break;

@@ -1059,6 +1062,8 @@ static __init int intel_pmu_init(void)
 
 		x86_pmu.event_constraints = intel_westmere_event_constraints;
 		x86_pmu.enable_all = intel_pmu_nhm_enable_all;
+		x86_pmu.pebs_constraints =
+				intel_westmere_pebs_event_constraints;
 		pr_cont("Westmere events, ");
 		break;

arch/x86/kernel/cpu/perf_event_intel_ds.c +38 ~~-21~~

88 lines not on this page · raw message

Lin Ming

2011-03-02 00:56 UTC #1 lore raw

Quoted 9 lines · Stephane Eranian

This patch updates PEBS event constraints for Intel Atom, Nehalem, Westmere.
This patch also reorganizes the PEBS format/constraint detection code. It is now based on processor model and not PEBS format. Two processors may use the same PEBS format without have the same list of PEBS events.
In this second version, we simplified the initialization of the PEBS constraints by leveraging the existing switch() statement in perf_event_intel.c. We also renamed the constraint tables to be more consistent with regular constraints.

Hi, Stephane

Nice updates.
Wondering where did you get these PEBS event constraints? I didn't find these in the latest manual.

And some small things, see below.

Quoted 80 lines

Signed-off-by Stephane Eranian <[email protected]>

---

arch/x86/kernel/cpu/perf_event_intel.c +5 -0

index 084b383..ddf6c4f 100644
@@ -1024,6 +1024,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_core();
 
 		x86_pmu.event_constraints = intel_core2_event_constraints;
+		x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
 		pr_cont("Core2 events, ");
 		break;

@@ -1036,6 +1037,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_nhm();
 
 		x86_pmu.event_constraints = intel_nehalem_event_constraints;
+		x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
 		x86_pmu.enable_all = intel_pmu_nhm_enable_all;
 		pr_cont("Nehalem events, ");
 		break;

@@ -1047,6 +1049,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_atom();
 
 		x86_pmu.event_constraints = intel_gen_event_constraints;
+		x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
 		pr_cont("Atom events, ");
 		break;

@@ -1059,6 +1062,8 @@ static __init int intel_pmu_init(void)
 
 		x86_pmu.event_constraints = intel_westmere_event_constraints;
 		x86_pmu.enable_all = intel_pmu_nhm_enable_all;
+		x86_pmu.pebs_constraints =
+				intel_westmere_pebs_event_constraints;
 		pr_cont("Westmere events, ");
 		break;

arch/x86/kernel/cpu/perf_event_intel_ds.c +10 ~~-14~~

index b7dcd9f..916e6c7 100644
@@ -361,30 +361,49 @@ static int intel_pmu_drain_bts_buffer(void)
 /*
  * PEBS
  */
-
-static struct event_constraint intel_core_pebs_events[] = {
+static struct event_constraint intel_core2_pebs_event_constraints[] = {
 	PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
 	PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 	PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 	PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
-	PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
-	PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
-	PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
-	PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
-	PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
+	INTEL_EVENT_CONSTRAINT(0xcb, 0x1),  /* MEM_LOAD_RETIRED.* */
+	EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_atom_pebs_event_constraints[] = {
+	PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
+	PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
+	PEBS_EVENT_CONSTRAINT(0x0ac4, 0x1), /* BR_INST_RETIRED.MISPRED */
+	INTEL_EVENT_CONSTRAINT(0xcb, 0x1),  /* MEM_LOAD_RETIRED.* */
 	EVENT_CONSTRAINT_END
 };
 
-static struct event_constraint intel_nehalem_pebs_events[] = {
-	PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
-	PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
-	PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
-	PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
-	PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
-	PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */

arch/x86/kernel/cpu/perf_event_intel_ds.c static int intel_pmu_drain_bts_buffer(void) · line 387

Quoted 10 lines

arch/x86/kernel/cpu/perf_event_intel_ds.c +7 -3

-	PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
-	PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
-	PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
+static struct event_constraint intel_nehalem_pebs_event_constraints[] = {
+	INTEL_EVENT_CONSTRAINT(0x0b, 0xf),  /* MEM_INST_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0x0f, 0xf),  /* MEM_UNCORE_RETIRED.* */
+	PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
+	INTEL_EVENT_CONSTRAINT(0xc0, 0xf),  /* INST_RETIRED.ANY */
+	INTEL_EVENT_CONSTRAINT(0xc2, 0xf),  /* UOPS_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0x00c4, 0xf),/* BR_INST_RETIRED.* */

- INTEL_EVENT_CONSTRAINT(0x00c4, 0xf)
+ INTEL_EVENT_CONSTRAINT(0xc4, 0xf)

Quoted 30 lines

arch/x86/kernel/cpu/perf_event_intel_ds.c +19 -1

+	PEBS_EVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
+	INTEL_EVENT_CONSTRAINT(0xc7, 0xf),  /* SSEX_UOPS_RETIRED.* */
+	PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
+	INTEL_EVENT_CONSTRAINT(0xcb, 0xf),  /* MEM_LOAD_RETIRED.* */
+	EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_westmere_pebs_event_constraints[] = {
+	INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
+	PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
+	INTEL_EVENT_CONSTRAINT(0xc0, 0xf),  /* INSTR_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xc2, 0xf),  /* UOPS_RETIRED.* */
+
+	INTEL_EVENT_CONSTRAINT(0xc4, 0xf),  /* BR_INST_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xc5, 0xf),  /* BR_MISP_RETIRED.* */
+	INTEL_EVENT_CONSTRAINT(0xc7, 0xf),  /* SSEX_UOPS_RETIRED.* */
+	PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
+	INTEL_EVENT_CONSTRAINT(0xcb, 0xf),  /* MEM_LOAD_RETIRED.* */
 	EVENT_CONSTRAINT_END
 };

@@ -695,20 +714,18 @@ static void intel_ds_init(void)
 			printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
 			x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
 			x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
-			x86_pmu.pebs_constraints = intel_core_pebs_events;
 			break;
 
 		case 1:

arch/x86/kernel/cpu/perf_event_intel_ds.c static void intel_ds_init(void) · line 727

Quoted 10 lines

arch/x86/kernel/cpu/perf_event_intel_ds.c +2 -2

 			printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
 			x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
 			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
-			x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
 			break;
 
 		default:
-			printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
+			printk(KERN_CONT "no PEBS fmt%d%c, ",
+			       format, pebs_type);

No changes?

Quoted 5 lines

arch/x86/kernel/cpu/perf_event_intel_ds.c +0 -1
 			x86_pmu.pebs = 0;
-			break;
 		}
 	}
 }

Stephane Eranian

author

2011-03-02 07:45 UTC #2 lore raw

Quoted 11 lines · Lin Ming

Quoted 9 lines · Stephane Eranian
This patch updates PEBS event constraints for Intel Atom, Nehalem, Westmere.
This patch also reorganizes the PEBS format/constraint detection code. It is now based on processor model and not PEBS format. Two processors may use the same PEBS format without have the same list of PEBS events.
In this second version, we simplified the initialization of the PEBS constraints by leveraging the existing switch() statement in perf_event_intel.c. We also renamed the constraint tables to be more consistent with regular constraints.

Quoted 6 lines

Hi, Stephane
Nice updates.
Wondering where did you get these PEBS event constraints? I didn't find these in the latest manual.

Yeah, the manual is lacking some information. The other source of information is the PTU event files (whatif.intel.com).

Quoted 87 lines

And some small things, see below.

Quoted 85 lines

Signed-off-by Stephane Eranian <[email protected]>

---

arch/x86/kernel/cpu/perf_event_intel.c +5 -0

index 084b383..ddf6c4f 100644
@@ -1024,6 +1024,7 @@ static __init int intel_pmu_init(void)
               intel_pmu_lbr_init_core();
 
               x86_pmu.event_constraints = intel_core2_event_constraints;
+             x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
               pr_cont("Core2 events, ");
               break;

@@ -1036,6 +1037,7 @@ static __init int intel_pmu_init(void)
               intel_pmu_lbr_init_nhm();
 
               x86_pmu.event_constraints = intel_nehalem_event_constraints;
+             x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
               x86_pmu.enable_all = intel_pmu_nhm_enable_all;
               pr_cont("Nehalem events, ");
               break;

@@ -1047,6 +1049,7 @@ static __init int intel_pmu_init(void)
               intel_pmu_lbr_init_atom();
 
               x86_pmu.event_constraints = intel_gen_event_constraints;
+             x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
               pr_cont("Atom events, ");
               break;

@@ -1059,6 +1062,8 @@ static __init int intel_pmu_init(void)
 
               x86_pmu.event_constraints = intel_westmere_event_constraints;
               x86_pmu.enable_all = intel_pmu_nhm_enable_all;
+             x86_pmu.pebs_constraints =
+                             intel_westmere_pebs_event_constraints;
               pr_cont("Westmere events, ");
               break;

arch/x86/kernel/cpu/perf_event_intel_ds.c +1 -2

index b7dcd9f..916e6c7 100644
@@ -361,30 +361,49 @@ static int intel_pmu_drain_bts_buffer(void)
  /*
   * PEBS
   */
-
-static struct event_constraint intel_core_pebs_events[] = {
+static struct event_constraint intel_core2_pebs_event_constraints[] = {

PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */ PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
- PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
- PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
- PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
- PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
- PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
+ INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
+ EVENT_CONSTRAINT_END

arch/x86/kernel/cpu/perf_event_intel_ds.c +7 -0

+};
+
+static struct event_constraint intel_atom_pebs_event_constraints[] = {
+     PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
+     PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
+     PEBS_EVENT_CONSTRAINT(0x0ac4, 0x1), /* BR_INST_RETIRED.MISPRED */
+     INTEL_EVENT_CONSTRAINT(0xcb, 0x1),  /* MEM_LOAD_RETIRED.* */

EVENT_CONSTRAINT_END
};

arch/x86/kernel/cpu/perf_event_intel_ds.c +2 ~~-10~~

-static struct event_constraint intel_nehalem_pebs_events[] = {
-     PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
-     PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
-     PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
-     PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
-     PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
-     PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
-     PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
-     PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
-     PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
+static struct event_constraint intel_nehalem_pebs_event_constraints[] = {
+     INTEL_EVENT_CONSTRAINT(0x0b, 0xf),  /* MEM_INST_RETIRED.* */

Quoted 9 lines

Quoted 5 lines
+ INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
+ PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
+ INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
+ INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
+ INTEL_EVENT_CONSTRAINT(0x00c4, 0xf),/* BR_INST_RETIRED.* */
- INTEL_EVENT_CONSTRAINT(0x00c4, 0xf)
+ INTEL_EVENT_CONSTRAINT(0xc4, 0xf)

yep.

Quoted 51 lines

Quoted 36 lines
+ PEBS_EVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
+ INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
+ PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
+ INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
+ EVENT_CONSTRAINT_END
arch/x86/kernel/cpu/perf_event_intel_ds.c +14 -0
+};
+
+static struct event_constraint intel_westmere_pebs_event_constraints[] = {
+     INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
+     INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
+     PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
+     INTEL_EVENT_CONSTRAINT(0xc0, 0xf),  /* INSTR_RETIRED.* */
+     INTEL_EVENT_CONSTRAINT(0xc2, 0xf),  /* UOPS_RETIRED.* */
+
+     INTEL_EVENT_CONSTRAINT(0xc4, 0xf),  /* BR_INST_RETIRED.* */
+     INTEL_EVENT_CONSTRAINT(0xc5, 0xf),  /* BR_MISP_RETIRED.* */
+     INTEL_EVENT_CONSTRAINT(0xc7, 0xf),  /* SSEX_UOPS_RETIRED.* */
+     PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
+     INTEL_EVENT_CONSTRAINT(0xcb, 0xf),  /* MEM_LOAD_RETIRED.* */
EVENT_CONSTRAINT_END
};
arch/x86/kernel/cpu/perf_event_intel_ds.c +0 -1
@@ -695,20 +714,18 @@ static void intel_ds_init(void)
                       printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
                       x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
                       x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
-                     x86_pmu.pebs_constraints = intel_core_pebs_events;
                       break;
 
case 1:
printk(KERN_CONT "PEBS fmt1%c, ", pebs_type); x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
- x86_pmu.pebs_constraints = intel_nehalem_pebs_events; break;
Quoted 4 lines
default:
- printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
+ printk(KERN_CONT "no PEBS fmt%d%c, ",
+ format, pebs_type);
No changes?
Quoted 5 lines
x86_pmu.pebs = 0;
- break;
}
}
}

Ingo Molnar

2011-03-02 08:14 UTC #3 lore raw

Quoted 12 lines · Stephane Eranian

Quoted 11 lines · Lin Ming
Quoted 9 lines · Stephane Eranian
This patch updates PEBS event constraints for Intel Atom, Nehalem, Westmere.
This patch also reorganizes the PEBS format/constraint detection code. It is now based on processor model and not PEBS format. Two processors may use the same PEBS format without have the same list of PEBS events.
In this second version, we simplified the initialization of the PEBS constraints by leveraging the existing switch() statement in perf_event_intel.c. We also renamed the constraint tables to be more consistent with regular constraints.

Quoted 8 lines

Quoted 6 lines
Hi, Stephane
Nice updates.
Wondering where did you get these PEBS event constraints? I didn't find these in the latest manual.
Yeah, the manual is lacking some information. The other source of information is the PTU event files (whatif.intel.com).

Plus i suspect you have performed testing on affected CPUs as well?

If yes then i think we want to push these fixes via perf/urgent - they seem to nicely round up the constraints.

Thanks,

Ingo

Stephane Eranian

author

2011-03-04 21:19 UTC #4 lore raw

Sorry for the delay. I realize I did not answer this message earlier.

Quoted 17 lines · Ingo Molnar

Quoted 14 lines · Stephane Eranian
Quoted 13 lines · Lin Ming
Quoted 9 lines · Stephane Eranian
This patch updates PEBS event constraints for Intel Atom, Nehalem, Westmere.
This patch also reorganizes the PEBS format/constraint detection code. It is now based on processor model and not PEBS format. Two processors may use the same PEBS format without have the same list of PEBS events.
In this second version, we simplified the initialization of the PEBS constraints by leveraging the existing switch() statement in perf_event_intel.c. We also renamed the constraint tables to be more consistent with regular constraints.
Hi, Stephane

Quoted 9 lines

Quoted 6 lines
Quoted 4 lines
Nice updates.
Wondering where did you get these PEBS event constraints? I didn't find these in the latest manual.
Yeah, the manual is lacking some information. The other source of information is the PTU event files (whatif.intel.com).
Plus i suspect you have performed testing on affected CPUs as well?

Yes, I did.

Quoted 7 lines

If yes then i think we want to push these fixes via perf/urgent - they seem to nicely round up the constraints.
Thanks,
Ingo