mmc: dw-mmc: add the header file for exynos specific code.

PATCH Superseded Jaehoon Chung 3 participants 7 messages Aug 23, 2012 – Aug 27, 2012

Subsystems (2)

Arm Samsung Exynos MMC, SD and SDIO

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Jaehoon Chung

author

2012-08-23 11:32 UTC #0 lore raw

PATCH 4/5 mmc: dw-mmc: add the header file for exynos specific code.

Signed-off-by Jaehoon Chung <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
 include/linux/mmc/exynos-dw_mmc.h |   55 +++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mmc/exynos-dw_mmc.h

include/linux/mmc/exynos-dw_mmc.h new file +55 -0

new file mode 100644
index 0000000..03444c2
@@ -0,0 +1,55 @@
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Header file for Exynos specific register
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EXYNOS_DW_MMC_H
+#define _EXYNOS_DW_MMC_H
+#include <linux/mmc/dw_mmc.h>
+#include <linux/mmc/host.h>
+
+#define SDMMC_EXYNOS_CLKSEL	0x09C
+
+#define SDMMC_GET_CLK_DRV(x)		((x) >> 16 & 0x7)
+#define SDMMC_GET_CLK_SAMPLE(x)		((x) & 0x7)
+#define SDMMC_CLK_RESET_DRV_SAMPLE	(0x00070007);
+
+#define mci_readl(dev, reg)			\
+	__raw_readl((dev)->regs + SDMMC_##reg)
+#define mci_writel(dev, reg, value)			\
+	__raw_writel((value), (dev)->regs + SDMMC_##reg)
+
+static inline int exynos_get_clk_drv(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline int exynos_get_clk_sample(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline void exynos_set_clk_drv_sample(struct dw_mci *host,
+		struct mmc_ios *ios)
+{
+	u32 regs;
+
+	regs = mci_readl(host, EXYNOS_CLKSEL);
+	regs &= ~SDMMC_CLK_RESET_DRV_SAMPLE;
+	if (ios->timing == MMC_TIMING_UHS_DDR50)
+		regs |= host->pdata->ddr_timing;
+	else
+		regs |= host->pdata->sdr_timing;
+
+	mci_writel(host, EXYNOS_CLKSEL, regs);
+}
+
+#endif /* _EXYNOS_DW_MMC_H */

Signature · 1 line

1.7.4.1

Seungwon Jeon

2012-08-24 03:57 UTC #1 lore raw

Quoted 26 lines · Jaehoon Chung

Signed-off-by Jaehoon Chung <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
 include/linux/mmc/exynos-dw_mmc.h |   55 +++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mmc/exynos-dw_mmc.h

include/linux/mmc/exynos-dw_mmc.h new file +13 -0

new file mode 100644
index 0000000..03444c2
@@ -0,0 +1,55 @@
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Header file for Exynos specific register
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+

include/linux/mmc/exynos-dw_mmc.h line 23

Quoted 10 lines

include/linux/mmc/exynos-dw_mmc.h new file +10 -0

+#ifndef _EXYNOS_DW_MMC_H
+#define _EXYNOS_DW_MMC_H
+#include <linux/mmc/dw_mmc.h>
+#include <linux/mmc/host.h>
+
+#define SDMMC_EXYNOS_CLKSEL	0x09C
+
+#define SDMMC_GET_CLK_DRV(x)		((x) >> 16 & 0x7)
+#define SDMMC_GET_CLK_SAMPLE(x)		((x) & 0x7)
+#define SDMMC_CLK_RESET_DRV_SAMPLE	(0x00070007);

Could you check the width of register field?
There is some difference between ExynosX.
It should cover all.

Quoted 38 lines

include/linux/mmc/exynos-dw_mmc.h new file +32 -1

+
+#define mci_readl(dev, reg)			\
+	__raw_readl((dev)->regs + SDMMC_##reg)
+#define mci_writel(dev, reg, value)			\
+	__raw_writel((value), (dev)->regs + SDMMC_##reg)
+
+static inline int exynos_get_clk_drv(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline int exynos_get_clk_sample(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline void exynos_set_clk_drv_sample(struct dw_mci *host,
+		struct mmc_ios *ios)
+{
+	u32 regs;
+
+	regs = mci_readl(host, EXYNOS_CLKSEL);
+	regs &= ~SDMMC_CLK_RESET_DRV_SAMPLE;
+	if (ios->timing == MMC_TIMING_UHS_DDR50)
+		regs |= host->pdata->ddr_timing;
+	else
+		regs |= host->pdata->sdr_timing;
+
+	mci_writel(host, EXYNOS_CLKSEL, regs);
+}
+
+#endif /* _EXYNOS_DW_MMC_H */
--

1.7.4.1
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Jaehoon Chung

author

2012-08-24 04:58 UTC #2 lore raw

Quoted 32 lines · Seungwon Jeon

Quoted 31 lines · Jaehoon Chung

Signed-off-by Jaehoon Chung <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
 include/linux/mmc/exynos-dw_mmc.h |   55 +++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mmc/exynos-dw_mmc.h

include/linux/mmc/exynos-dw_mmc.h new file +18 -0

new file mode 100644
index 0000000..03444c2
@@ -0,0 +1,55 @@
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Header file for Exynos specific register
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EXYNOS_DW_MMC_H
+#define _EXYNOS_DW_MMC_H
+#include <linux/mmc/dw_mmc.h>
+#include <linux/mmc/host.h>
+

Quoted 8 lines

include/linux/mmc/exynos-dw_mmc.h line 23
Quoted 5 lines
include/linux/mmc/exynos-dw_mmc.h new file +5 -0
+#define SDMMC_EXYNOS_CLKSEL	0x09C
+
+#define SDMMC_GET_CLK_DRV(x)		((x) >> 16 & 0x7)
+#define SDMMC_GET_CLK_SAMPLE(x)		((x) & 0x7)
+#define SDMMC_CLK_RESET_DRV_SAMPLE	(0x00070007);
Could you check the width of register field?
There is some difference between ExynosX.
It should cover all.

I checked the Exynos4 and Exynos5.
So i used the 0x7.
If i miss something, let me know.

Best Regards,
Jaehoon Chung

Quoted 45 lines

Quoted 34 lines
include/linux/mmc/exynos-dw_mmc.h new file +32 -1
+
+#define mci_readl(dev, reg)			\
+	__raw_readl((dev)->regs + SDMMC_##reg)
+#define mci_writel(dev, reg, value)			\
+	__raw_writel((value), (dev)->regs + SDMMC_##reg)
+
+static inline int exynos_get_clk_drv(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline int exynos_get_clk_sample(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline void exynos_set_clk_drv_sample(struct dw_mci *host,
+		struct mmc_ios *ios)
+{
+	u32 regs;
+
+	regs = mci_readl(host, EXYNOS_CLKSEL);
+	regs &= ~SDMMC_CLK_RESET_DRV_SAMPLE;
+	if (ios->timing == MMC_TIMING_UHS_DDR50)
+		regs |= host->pdata->ddr_timing;
+	else
+		regs |= host->pdata->sdr_timing;
+
+	mci_writel(host, EXYNOS_CLKSEL, regs);
+}
+
+#endif /* _EXYNOS_DW_MMC_H */
--
Quoted 5 lines
1.7.4.1
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Seungwon Jeon

2012-08-27 01:28 UTC #3 lore raw

Quoted 41 lines · Jaehoon Chung

Quoted 32 lines · Seungwon Jeon

Quoted 31 lines · Jaehoon Chung

Signed-off-by Jaehoon Chung <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
 include/linux/mmc/exynos-dw_mmc.h |   55 +++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mmc/exynos-dw_mmc.h

include/linux/mmc/exynos-dw_mmc.h new file +18 -0

new file mode 100644
index 0000000..03444c2
@@ -0,0 +1,55 @@
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Header file for Exynos specific register
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EXYNOS_DW_MMC_H
+#define _EXYNOS_DW_MMC_H
+#include <linux/mmc/dw_mmc.h>
+#include <linux/mmc/host.h>
+

Quoted 8 lines

include/linux/mmc/exynos-dw_mmc.h line 23
Quoted 5 lines
include/linux/mmc/exynos-dw_mmc.h new file +5 -0
+#define SDMMC_EXYNOS_CLKSEL	0x09C
+
+#define SDMMC_GET_CLK_DRV(x)		((x) >> 16 & 0x7)
+#define SDMMC_GET_CLK_SAMPLE(x)		((x) & 0x7)
+#define SDMMC_CLK_RESET_DRV_SAMPLE	(0x00070007);
Could you check the width of register field?
There is some difference between ExynosX.
It should cover all.

Quoted 3 lines

I checked the Exynos4 and Exynos5.
So i used the 0x7.
If i miss something, let me know.

In case of Eyxnos4210, only 2 bits are used.
And new field(DIVRATIO) is added in Exynos5.
It needs to check DIVRATIO for SDMMC_CLK_RESET_DRV_SAMPLE.

Thanks,
Seungwon Jeon.

Quoted 53 lines

Best Regards,
Jaehoon Chung
Quoted 36 lines
Quoted 36 lines
include/linux/mmc/exynos-dw_mmc.h new file +32 -1
+
+#define mci_readl(dev, reg)			\
+	__raw_readl((dev)->regs + SDMMC_##reg)
+#define mci_writel(dev, reg, value)			\
+	__raw_writel((value), (dev)->regs + SDMMC_##reg)
+
+static inline int exynos_get_clk_drv(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline int exynos_get_clk_sample(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline void exynos_set_clk_drv_sample(struct dw_mci *host,
+		struct mmc_ios *ios)
+{
+	u32 regs;
+
+	regs = mci_readl(host, EXYNOS_CLKSEL);
+	regs &= ~SDMMC_CLK_RESET_DRV_SAMPLE;
+	if (ios->timing == MMC_TIMING_UHS_DDR50)
+		regs |= host->pdata->ddr_timing;
+	else
+		regs |= host->pdata->sdr_timing;
+
+	mci_writel(host, EXYNOS_CLKSEL, regs);
+}
+
+#endif /* _EXYNOS_DW_MMC_H */
--
1.7.4.1
--
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Jaehoon Chung

author

2012-08-27 01:48 UTC #4 lore raw

Quoted 42 lines · Seungwon Jeon

Quoted 41 lines · Jaehoon Chung

Quoted 40 lines · Seungwon Jeon

Quoted 26 lines · Jaehoon Chung

Signed-off-by Jaehoon Chung <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
 include/linux/mmc/exynos-dw_mmc.h |   55 +++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mmc/exynos-dw_mmc.h

include/linux/mmc/exynos-dw_mmc.h new file +13 -0

new file mode 100644
index 0000000..03444c2
@@ -0,0 +1,55 @@
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Header file for Exynos specific register
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+

include/linux/mmc/exynos-dw_mmc.h line 23

Quoted 10 lines

include/linux/mmc/exynos-dw_mmc.h new file +10 -0

+#ifndef _EXYNOS_DW_MMC_H
+#define _EXYNOS_DW_MMC_H
+#include <linux/mmc/dw_mmc.h>
+#include <linux/mmc/host.h>
+
+#define SDMMC_EXYNOS_CLKSEL	0x09C
+
+#define SDMMC_GET_CLK_DRV(x)		((x) >> 16 & 0x7)
+#define SDMMC_GET_CLK_SAMPLE(x)		((x) & 0x7)
+#define SDMMC_CLK_RESET_DRV_SAMPLE	(0x00070007);

Could you check the width of register field?
There is some difference between ExynosX.
It should cover all.

Quoted 6 lines

Quoted 3 lines
I checked the Exynos4 and Exynos5.
So i used the 0x7.
If i miss something, let me know.
In case of Eyxnos4210, only 2 bits are used.
And new field(DIVRATIO) is added in Exynos5.
It needs to check DIVRATIO for SDMMC_CLK_RESET_DRV_SAMPLE.

I understood yours.
I will resend the patch.

Best Regards,
Jaehoon Chung

Quoted 62 lines

Thanks,
Seungwon Jeon.
Quoted 49 lines
Best Regards,
Jaehoon Chung
Quoted 36 lines
Quoted 36 lines
include/linux/mmc/exynos-dw_mmc.h new file +32 -1
+
+#define mci_readl(dev, reg)			\
+	__raw_readl((dev)->regs + SDMMC_##reg)
+#define mci_writel(dev, reg, value)			\
+	__raw_writel((value), (dev)->regs + SDMMC_##reg)
+
+static inline int exynos_get_clk_drv(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline int exynos_get_clk_sample(struct dw_mci *host)
+{
+	return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
+}
+
+static inline void exynos_set_clk_drv_sample(struct dw_mci *host,
+		struct mmc_ios *ios)
+{
+	u32 regs;
+
+	regs = mci_readl(host, EXYNOS_CLKSEL);
+	regs &= ~SDMMC_CLK_RESET_DRV_SAMPLE;
+	if (ios->timing == MMC_TIMING_UHS_DDR50)
+		regs |= host->pdata->ddr_timing;
+	else
+		regs |= host->pdata->sdr_timing;
+
+	mci_writel(host, EXYNOS_CLKSEL, regs);
+}
+
+#endif /* _EXYNOS_DW_MMC_H */
--
1.7.4.1
--
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Quoted 4 lines
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Will Newton

2012-08-24 09:29 UTC #5 lore raw

In reply to Jaehoon Chung

On Thu, Aug 23, 2012 at 12:31 PM, Jaehoon Chung <[email protected]> wrote:

Hi Jaehoon,

Quoted 6 lines

Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 include/linux/mmc/exynos-dw_mmc.h |   55 +++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mmc/exynos-dw_mmc.h

What is the purpose of adding this header file if it is not included anywhere? Is there a patch missing from the series?

Jaehoon Chung

author

2012-08-24 09:36 UTC #6 lore raw

Hi Will

Quoted 11 lines · Will Newton

On Thu, Aug 23, 2012 at 12:31 PM, Jaehoon Chung <[email protected]> wrote:
Hi Jaehoon,
Quoted 6 lines
Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 include/linux/mmc/exynos-dw_mmc.h |   55 +++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mmc/exynos-dw_mmc.h

Quoted 2 lines

What is the purpose of adding this header file if it is not included anywhere? Is there a patch missing from the series?

I will send to add the patch in the next version.
This header should be included into board file related with exynos4 or exynos5. Thank you for comment.

Best Regards,
Jaehoon Chung

Quoted 5 lines

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