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SMP Documentation?

DISCUSSION Kent Borg 2 participants 3 messages Mar 7, 2014 – Mar 11, 2014

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Kent Borg

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Is there any documentation on the semantics of the SMP ops:

- .smp_init_cpus,
- .smp_prepare_cpus,
- .smp_secondary_init,
- .smp_boot_secondary?

I can certainly see examples in existing code, but I isn't clear to me why, for example, an SoC can't just do everything in smp_boot_secondary()?

Thanks,

-kb, the Kent who figures these four different calls are there for reasons, and there are a lot of ways for SMP to not work if he doesn't understand the reasons.

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Quoted 1 line · On 03/07/2014 06:14 PM, I wrote:

Is there any documentation on the semantics of the SMP ops

<crickets>

It seems there is not any documentation, and no one has lept forward to write some for little ol' me.

But fear not! I noticed mention the SMP work for rockchip going by on the list...and it looks analogous to what I need to do. So I am going to start cribbing from that.

Thanks,

-kb, the Kent who, alas, will still probably darken your inbox in the future.

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Kent,

2014-03-11 3:22 GMT+08:00 Kent Borg <[email protected]>:

Quoted 5 lines · On 03/07/2014 06:14 PM, I wrote:
Quoted 2 lines

Is there any documentation on the semantics of the SMP ops

Quoted 8 lines

<crickets>

It seems there is not any documentation, and no one has lept forward to write some for little ol' me.

But fear not! I noticed mention the SMP work for rockchip going by on the list...and it looks analogous to what I need to do. So I am going to start cribbing from that.

you can read CSR codes for marco. we have one struct smp_operations sirfsoc_smp_ops __initdata = {

        .smp_prepare_cpus       = sirfsoc_smp_prepare_cpus,
        .smp_secondary_init     = sirfsoc_secondary_init,
        .smp_boot_secondary     = sirfsoc_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = sirfsoc_cpu_die,
#endif
};

in sirfsoc_smp_prepare_cpus, we enable SCU for cache coherence of SMP,
sirfsoc_secondary_init() is executed by 2nd core which will clear
pen_release.
sirfsoc_boot_secondary is the code for the cpu0 to wake up the 2nd core, after waking, the cpu0 will wait for 2nd core to set pen_release to -1.

Quoted 7 lines

Thanks,

-kb, the Kent who, alas, will still probably darken your inbox in the future.

-barry