arch/unicore32/kernel/clock.c: add readl() and writel() for 'PM_' macros

Hello all:

As far as I know, unicore32 is still alive. If it will be obsoleted, please let me know, so we can avoid the related spam about unicored32 (also can save my time resource).

Thanks.

Signature · 3 lines

Chen Gang

Open, share, and attitude like air, water, and life which God blessed

Sorry for replying so late.
I'd like to ack the patch after testing it.
Maybe before this weekend.

Thanks Chen.

Xuetao Guan

Quoted 7 lines · ----- Chen Gang

Hello all:

As far as I know, unicore32 is still alive. If it will be obsoleted, please let me know, so we can avoid the related spam about unicored32 (also can save my time resource).

Add readl() and writel() for 'PM_' macros, just like another areas have done within unicored32, or will cause compiling issue.

The related error (allmodconfig for unicored32):

CC arch/unicore32/kernel/clock.o
arch/unicore32/kernel/clock.c: In function ‘clk_set_rate’:
arch/unicore32/kernel/clock.c:182: warning: initialization makes integer from pointer without a cast arch/unicore32/kernel/clock.c:204: error: lvalue required as left operand of assignment arch/unicore32/kernel/clock.c:206: error: lvalue required as left operand of assignment arch/unicore32/kernel/clock.c:207: error: invalid operands to binary & (have ‘void *’ and ‘long unsigned int’) make[1]: *** [arch/unicore32/kernel/clock.o] Error 1
make: *** [arch/unicore32/kernel] Error 2

Signed-off-by Chen Gang <[email protected]>

---
 arch/unicore32/kernel/clock.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

arch/unicore32/kernel/clock.c +4 -4

index 18d4563..b1ca775 100644
@@ -179,7 +179,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 	}
 #ifdef CONFIG_CPU_FREQ
 	if (clk == &clk_mclk_clk) {
-		u32 pll_rate, divstatus = PM_DIVSTATUS;
+		u32 pll_rate, divstatus = readl(PM_DIVSTATUS);
 		int ret, i;
 
 		/* lookup mclk_clk_table */

@@ -201,10 +201,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 				/ (((divstatus & 0x0000f000) >> 12) + 1);
 
 		/* set pll sys cfg reg. */
-		PM_PLLSYSCFG = pll_rate;
+		writel(pll_rate, PM_PLLSYSCFG);
 
-		PM_PMCR = PM_PMCR_CFBSYS;
-		while ((PM_PLLDFCDONE & PM_PLLDFCDONE_SYSDFC)
+		writel(PM_PMCR_CFBSYS, PM_PMCR);
+		while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_SYSDFC)
 				!= PM_PLLDFCDONE_SYSDFC)
 			udelay(100);
 			/* about 1ms */

Signature · 1 line

1.7.9.5