pci: Use bus master address space for delivering MSI/MSI-X messages
PATCH 1/1 pci: Use bus master address space for delivering MSI/MSI-X messages
From: Jan Kiszka <[email protected]>
The spec says (and real HW confirms this) that, if the bus master bit is 0, the device will not generate any PCI accesses. MSI and MSI-X messages fall among these, so we should use the corresponding address space to deliver them. This will prevent delivery if bus master support is disabled.
--- hw/pci/msi.c | 2 +- hw/pci/msix.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
hw/pci/msi.c +1 -1
@@ -291,7 +291,7 @@ void msi_notify(PCIDevice *dev, unsigned int vector)"notify vector 0x%x" " address: 0x%" PRIx64" data: 0x%" PRIx32"\n" , vector, msg.address, msg.data); -stl_le_phys (&address_space_memory, msg.address, msg.data); +stl_le_phys (&dev->bus_master_as, msg.address, msg.data); }/* Normally called by pci_default_write_config(). */
hw/pci/msix.c +1 -1
@@ -439,7 +439,7 @@ void msix_notify(PCIDevice *dev, unsigned vector) msg =msix_get_message (dev, vector); -stl_le_phys (&address_space_memory, msg.address, msg.data); +stl_le_phys (&dev->bus_master_as, msg.address, msg.data); }void msix_reset (PCIDevice *dev)
Signature · 1 line
1.8.1.1.298.ge7eed54
Il 27/07/2014 09:08, Jan Kiszka ha scritto:
Quoted 33 lines
From: Jan Kiszka <[email protected]>
The spec says (and real HW confirms this) that, if the bus master bit is 0, the device will not generate any PCI accesses. MSI and MSI-X messages fall among these, so we should use the corresponding address space to deliver them. This will prevent delivery if bus master support is disabled.
Signed-off-by Jan Kiszka <[email protected]>--- hw/pci/msi.c | 2 +- hw/pci/msix.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)hw/pci/msi.c +1
-1@@ -291,7 +291,7 @@ void msi_notify(PCIDevice *dev, unsigned int vector)"notify vector 0x%x" " address: 0x%" PRIx64" data: 0x%" PRIx32"\n" , vector, msg.address, msg.data); -stl_le_phys (&address_space_memory, msg.address, msg.data); +stl_le_phys (&dev->bus_master_as, msg.address, msg.data); }/* Normally called by pci_default_write_config(). */ hw/pci/msix.c +0
-0
hw/pci/msix.c void msix_notify(PCIDevice *dev, unsigned vector) · line 445
Quoted 8 lines
hw/pci/msix.c +1
-1@@ -439,7 +439,7 @@ void msix_notify(PCIDevice *dev, unsigned vector) msg =msix_get_message (dev, vector); -stl_le_phys (&address_space_memory, msg.address, msg.data); +stl_le_phys (&dev->bus_master_as, msg.address, msg.data); }void msix_reset (PCIDevice *dev)
Quoted 9 lines · Jan Kiszka
From: Jan Kiszka <[email protected]>
The spec says (and real HW confirms this) that, if the bus master bit is 0, the device will not generate any PCI accesses. MSI and MSI-X messages fall among these, so we should use the corresponding address space to deliver them. This will prevent delivery if bus master support is disabled.
Signed-off-by Jan Kiszka <[email protected]>
Pls remember to repost when 2.1 is out.
Thanks!
Quoted 34 lines
--- hw/pci/msi.c | 2 +- hw/pci/msix.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)hw/pci/msi.c +1
-1@@ -291,7 +291,7 @@ void msi_notify(PCIDevice *dev, unsigned int vector)"notify vector 0x%x" " address: 0x%" PRIx64" data: 0x%" PRIx32"\n" , vector, msg.address, msg.data); -stl_le_phys (&address_space_memory, msg.address, msg.data); +stl_le_phys (&dev->bus_master_as, msg.address, msg.data); }/* Normally called by pci_default_write_config(). */ hw/pci/msix.c +1
-1@@ -439,7 +439,7 @@ void msix_notify(PCIDevice *dev, unsigned vector) msg =msix_get_message (dev, vector); -stl_le_phys (&address_space_memory, msg.address, msg.data); +stl_le_phys (&dev->bus_master_as, msg.address, msg.data); }void msix_reset (PCIDevice *dev)Signature · 1 line
1.8.1.1.298.ge7eed54