imx6: ipu: wrong pixel clock

Hi,

First of all, I am not sure if this is the right mailinglist, but I couldn't find a imx specific one.

I am trying to get a small lcd working connected to the wandboard. I am currently at 2d65a9f48fcdf7866aab6457bc707ca233e0c791, with some small modifications as listed below.

The good thing is, this works. The not so nice thing is that the kernel thinks the lcd is driven at 9Mhz, but it is actually at around 21Mhz. When changing the clock to 8Mhz, the DI is used as pixel clock and the pixel clock is fine.

9Mhz -> actual 21 Mhz when measured

[    1.707543] imx-ipuv3 2400000.ipu: disp 0: panel size = 480 x 272
[    1.707568] imx-ipuv3 2400000.ipu: Clocks: IPU 264000000Hz DI 
24000000Hz Needed 9000000Hz
[    1.707672] imx-ipuv3 2400000.ipu:   IPU clock can give 9103448 with 
divider 29, error 1.1%
[    1.707889] imx-ipuv3 2400000.ipu: Want 9000000Hz IPU 264000000Hz DI 
9000000Hz using DI, 9000000Hz
[    1.708026] imx-ipuv3 2400000.ipu: dmfc: trying to allocate 7Mpixel/s 
for IPU channel 23
[    1.708038] imx-ipuv3 2400000.ipu: dmfc: freeing 0 slots starting 
from segment 0
[    1.708131] imx-ipuv3 2400000.ipu: dmfc: using 2 slots starting from 

segment 0 for IPU channel 23

8Mhz -> correct when measured

[    1.719676] imx-ipuv3 2400000.ipu: disp 0: panel size = 480 x 272
[    1.719701] imx-ipuv3 2400000.ipu: Clocks: IPU 264000000Hz DI 
24000000Hz Needed 8000000Hz
[    1.719796] imx-ipuv3 2400000.ipu:   IPU clock can give 8000000 with 
divider 33, error 0.0%
[    1.719825] imx-ipuv3 2400000.ipu: Want 8000000Hz IPU 264000000Hz DI 
24000000Hz using IPU, 8000000Hz
[    1.719954] imx-ipuv3 2400000.ipu: dmfc: trying to allocate 7Mpixel/s 
for IPU channel 23
[    1.719969] imx-ipuv3 2400000.ipu: dmfc: freeing 0 slots starting 
from segment 0
[    1.720062] imx-ipuv3 2400000.ipu: dmfc: using 2 slots starting from 

segment 0 for IPU channel 23

Am I missing something in the device tree or is there something wrong in linux/drivers/gpu/ipu-v3/ipu-di.c?

With kind regards,
Jeroen

+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
@@ -166,7 +169,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,

                 sig_cfg.Vsync_pol = 1;

         sig_cfg.enable_pol = 1;

- sig_cfg.clk_pol = 0;
+ sig_cfg.clk_pol = 1;

and

b/arch/arm/boot/dts/imx6q-wandboard.dts
index 4a8a6ee..3b90e2d 100644

I wonder if this is caused by the kernel's idea of the clock tree not being the same as what the clock tree actually is.

The IPU DI clock definitely does work as the code desires as it works with HDMI and definitely does produce the right clock rate.

The clue I think is that you can't end up with a 21MHz clock from a DI clock of 24MHz with an integer divider. So the clock rate which is believed to be from the DI isn't correct. I suspect a CCF/iMX problem.

FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.