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Make Octeon GPIO IRQ chip CPU hotplug-aware

PATCH In review Alexander Sverdlin 3 participants 3 messages Oct 23, 2014 MIPS

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#0 lore raw

PATCH 1/1 Make Octeon GPIO IRQ chip CPU hotplug-aware

From: Alexander Sverdlin <[email protected]>

Make Octeon GPIO IRQ chip CPU hotplug-aware

Seems that irq_cpu_offline callbacks were forgotten in v1 and v2 CIU GPIO chips. There is such a callback for octeon_irq_chip_ciu2_gpio, covering CIU2 chips. Without this callback GPIO IRQs are not being migrated during core offlining. Patch is tested on Octeon II.

---

arch/mips/cavium-octeon/octeon-irq.c +2 -0
@@ -809,6 +809,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
 	.irq_set_type = octeon_irq_ciu_gpio_set_type,
 #ifdef CONFIG_SMP
 	.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
+	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
 #endif
 	.flags = IRQCHIP_SET_TYPE_MASKED,
 };
@@ -823,6 +824,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = {
 	.irq_set_type = octeon_irq_ciu_gpio_set_type,
 #ifdef CONFIG_SMP
 	.irq_set_affinity = octeon_irq_ciu_set_affinity,
+	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
 #endif
 	.flags = IRQCHIP_SET_TYPE_MASKED,
 };
Acked-by on v1 1/1
#1 lore raw
Quoted 10 lines · Alexander Sverdlin

From: Alexander Sverdlin <[email protected]>

Make Octeon GPIO IRQ chip CPU hotplug-aware

Seems that irq_cpu_offline callbacks were forgotten in v1 and v2 CIU GPIO chips. There is such a callback for octeon_irq_chip_ciu2_gpio, covering CIU2 chips. Without this callback GPIO IRQs are not being migrated during core offlining. Patch is tested on Octeon II.

Ralf, please apply.

Thanks,
David Daney

Quoted 23 lines

---

arch/mips/cavium-octeon/octeon-irq.c +2 -0
@@ -809,6 +809,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
  	.irq_set_type = octeon_irq_ciu_gpio_set_type,
  #ifdef CONFIG_SMP
  	.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
+	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
  #endif
  	.flags = IRQCHIP_SET_TYPE_MASKED,
  };
@@ -823,6 +824,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = {
  	.irq_set_type = octeon_irq_ciu_gpio_set_type,
  #ifdef CONFIG_SMP
  	.irq_set_affinity = octeon_irq_ciu_set_affinity,
+	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
  #endif
  	.flags = IRQCHIP_SET_TYPE_MASKED,
  };
#2 lore raw
Quoted 17 lines · David Daney

Date: Thu, 23 Oct 2014 08:59:08 -0700
From: David Daney <[email protected]>
To: Alexander Sverdlin <[email protected]>
CC: [email protected], [email protected]
Subject: Re: [PATCH] Make Octeon GPIO IRQ chip CPU hotplug-aware
Content-Type: text/plain; charset=UTF-8; format=flowed

Quoted 9 lines · Alexander Sverdlin

From: Alexander Sverdlin <[email protected]>

Make Octeon GPIO IRQ chip CPU hotplug-aware

Seems that irq_cpu_offline callbacks were forgotten in v1 and v2 CIU GPIO chips. There is such a callback for octeon_irq_chip_ciu2_gpio, covering CIU2 chips. Without this callback GPIO IRQs are not being migrated during core offlining. Patch is tested on Octeon II.

Quoted 5 lines
Quoted 1 line

Ralf, please apply.

Already did that, so the commits won't have your ack.

Thanks for reviewing!

Ralf