clockevents: new material for 3.19
Hi Thomas,
This pull request contains the following changes:
* Ezequiel Garcia added the missing 'clock_enabled' calls before
getting the clocks' rate, switched to the reference clock for both the timer and the watchdog on a37, and updated the DT bindings documentation accordingly
* Yanchang Li removed the hard coded clock rate and let use the
configurable one
Thanks !
-- Daniel
The following changes since commit 867f667fb9c6734e06cc24e96fc7f06a7e772084:
Merge tag 'renesas-clocksource-for-v3.18' ofgit://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into clockevents/3.18 (2014-09-29 01:59:51 +0200)
are available in the git repository at:
http://git.linaro.org/people/daniel.lezcano/linux.git clockevents/3.19
for you to fetch changes up to 4a22d9c93af1f2b2c40354c4bc59fd007f33f05e:
clocksource: armada-370-xp: Use the reference clock on A375 SoC
(2014-11-26 13:51:08 +0100)
----------------------------------------------------------------
Ezequiel Garcia (3):
clocksource: armada-370-xp: Add missing clock enable
watchdog: orion: Use the reference clock on Armada 375 SoC
clocksource: armada-370-xp: Use the reference clock on A375 SoC
Yanchang Li (1):
clocksource: sirf: Remove hard-coded clock rate
Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt | 9 ++++++---
Documentation/devicetree/bindings/watchdog/marvel.txt
| 13 +++++++++++++
drivers/clocksource/time-armada-370-xp.c
| 30 ++++++++++++++++++++++++++++++
drivers/clocksource/timer-marco.c
| 23 +++++++++--------------
drivers/watchdog/orion_wdt.c
| 42 +++++++++++++++++++++++++++++++++++++++++-
5 files changed, 99 insertions(+), 18 deletions(-)
Signature · 5 lines
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PATCH 1/4 clocksource: sirf: Remove hard-coded clock rate
From: Yanchang Li <[email protected]>
The customers may want to adjust the whole PLL and dividers according to different user scenerios, and this causes the parent clock of sirf clocksource not be divided exactly by the current hard-coded 1MHz clock rate. This patch removes the hard-coded rate and makes the clocksource driver more adaptive to the external changes.
--- drivers/clocksource/timer-marco.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-)
drivers/clocksource/timer-marco.c +9 -14
@@ -20,8 +20,6 @@#include <linux/of_address.h> #include <linux/sched_clock.h> -#define MARCO_CLOCK_FREQ 1000000 -#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004#define SIRFSOC_TIMER_MATCH_0 0x0018
@@ -40,6 +38,8 @@#define SIRFSOC_TIMER_REG_CNT 6 +static unsigned long marco_timer_rate; +static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT ] = {SIRFSOC_TIMER_WATCHDOG_EN ,SIRFSOC_TIMER_32COUNTER_0_CTRL ,
@@ -195,7 +195,7 @@ static int sirfsoc_local_timer_setup(struct clock_event_device *ce) ce->rating =200 ; ce->set_mode = sirfsoc_timer_set_mode; ce->set_next_event = sirfsoc_timer_set_next_event; -clockevents_calc_mult_shift (ce,MARCO_CLOCK_FREQ ,60 ); +clockevents_calc_mult_shift (ce, marco_timer_rate,60 ); ce->max_delta_ns =clockevent_delta2ns (-2 , ce); ce->min_delta_ns =clockevent_delta2ns (2 , ce); ce->cpumask =cpumask_of (cpu);
@@ -257,7 +257,6 @@ static void __init sirfsoc_clockevent_init(void)/* initialize the kernel jiffy timer source */ static void __init sirfsoc_marco_timer_init (struct device_node *np) { -unsigned long rate;u32 timer_div;struct clk *clk;
@@ -266,16 +265,12 @@ static void __init sirfsoc_marco_timer_init(struct device_node *np)BUG_ON (clk_prepare_enable (clk)); - rate =clk_get_rate (clk); - -BUG_ON (rate <MARCO_CLOCK_FREQ ); -BUG_ON (rate %MARCO_CLOCK_FREQ ); + marco_timer_rate =clk_get_rate (clk); -/* Initialize the timer dividers */ - timer_div = rate /MARCO_CLOCK_FREQ -1 ; -writel_relaxed (timer_div <<16 , sirfsoc_timer_base +SIRFSOC_TIMER_64COUNTER_CTRL ); -writel_relaxed (timer_div <<16 , sirfsoc_timer_base +SIRFSOC_TIMER_32COUNTER_0_CTRL ); -writel_relaxed (timer_div <<16 , sirfsoc_timer_base +SIRFSOC_TIMER_32COUNTER_1_CTRL ); +/* timer dividers: 0, not divided */ +writel_relaxed (0 , sirfsoc_timer_base +SIRFSOC_TIMER_64COUNTER_CTRL ); +writel_relaxed (0 , sirfsoc_timer_base +SIRFSOC_TIMER_32COUNTER_0_CTRL ); +writel_relaxed (0 , sirfsoc_timer_base +SIRFSOC_TIMER_32COUNTER_1_CTRL );/* Initialize timer counters to 0 */ writel_relaxed (0 , sirfsoc_timer_base +SIRFSOC_TIMER_64COUNTER_LOAD_LO );
@@ -288,7 +283,7 @@ static void __init sirfsoc_marco_timer_init(struct device_node *np)/* Clear all interrupts */ writel_relaxed (0xFFFF , sirfsoc_timer_base +SIRFSOC_TIMER_INTR_STATUS ); -BUG_ON (clocksource_register_hz (&sirfsoc_clocksource,MARCO_CLOCK_FREQ )); +BUG_ON (clocksource_register_hz (&sirfsoc_clocksource, marco_timer_rate));sirfsoc_clockevent_init (); }
Signature · 1 line
1.9.1
PATCH 2/4 clocksource: armada-370-xp: Add missing clock enable
From: Ezequiel Garcia <[email protected]>
This commit makes sure the timer clock is prepared and enabled before retrieving its rate.
--- drivers/clocksource/time-armada-370-xp.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/clocksource/time-armada-370-xp.c +2 -0
@@ -293,6 +293,7 @@ static void __init armada_xp_timer_init(struct device_node *np)/* The 25Mhz fixed clock is mandatory, and must always be available */ BUG_ON (IS_ERR (clk)); +clk_prepare_enable (clk); timer_clk =clk_get_rate (clk);armada_370_xp_timer_common_init (np);
@@ -305,6 +306,7 @@ static void __init armada_370_timer_init(struct device_node *np)struct clk *clk =of_clk_get (np,0 );BUG_ON (IS_ERR (clk)); +clk_prepare_enable (clk); timer_clk =clk_get_rate (clk) /TIMER_DIVIDER ; timer25Mhz = false;
Signature · 1 line
1.9.1
PATCH 3/4 watchdog: orion: Use the reference clock on Armada 375 SoC
In reply to Daniel LezcanoFrom: Ezequiel Garcia <[email protected]>
The 25 MHz reference clock has better stability so its use is prefered over the core clock. Change the Armada 375 clock initialization to use this reference clock. To ensure the driver is compatible with an old devicetree, also provide a fallback path which will silently return to the previous behavior.
While here, add the clock specification to the binding documentation.
--- .../devicetree/bindings/watchdog/marvel.txt | 13 +++++++ drivers/watchdog/orion_wdt.c | 42 +++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/watchdog/marvel.txt +13 -0
@@ -17,6 +17,18 @@ For "marvell,armada-375-wdt" and "marvell,armada-380-wdt": - reg : A third entry is mandatory and should contain the shared mask/unmask RSTOUT address. +Clocks required for compatibles = "marvell,orion-wdt", + "marvell,armada-370-wdt": +- clocks : Must contain a single entry describing the clock input + +Clocks required for compatibles = "marvell,armada-xp-wdt" + "marvell,armada-375-wdt" + "marvell,armada-380-wdt": +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must include the following entries: + "nbclk" (L2/coherency fabric clock), + "fixed" (Reference 25 MHz fixed-clock). + Optional properties: - interrupts : Contains the IRQ for watchdog expiration
@@ -30,4 +42,5 @@ Example: interrupts = <3>; timeout-sec = <10>; status = "okay"; + clocks = <&gate_clk 7>; };
drivers/watchdog/orion_wdt.c +41 -1
54 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH 4/4 clocksource: armada-370-xp: Use the reference clock on A375 SoC
In reply to Daniel LezcanoFrom: Ezequiel Garcia <[email protected]>
The 25 MHz reference clock has better stability so its use is preferred over the core clock.
This commit takes advantage of the already introduced Armada 375 devicetree compatible string and adds a new timer initialization. If available, the timer will use the reference clock (named as 'fixed'). Otherwise, it falls back to the previous behavior.
--- .../bindings/timer/marvell,armada-370-xp-timer.txt | 9 ++++--- drivers/clocksource/time-armada-370-xp.c | 28 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt +6 -3
@@ -2,8 +2,10 @@ Marvell Armada 370 and Armada XP Timers --------------------------------------- Required properties: -- compatible: Should be either "marvell,armada-370-timer" or - "marvell,armada-xp-timer" as appropriate. +- compatible: Should be one of the following + "marvell,armada-370-timer", + "marvell,armada-375-timer", + "marvell,armada-xp-timer". - interrupts: Should contain the list of Global Timer interrupts and then local timer interrupts - reg: Should contain location and length for timers register. First
@@ -13,7 +15,8 @@ Required properties: Clocks required for compatible = "marvell,armada-370-timer": - clocks : Must contain a single entry describing the clock input -Clocks required for compatible = "marvell,armada-xp-timer": +Clocks required for compatibles = "marvell,armada-xp-timer", + "marvell,armada-375-timer": - clocks : Must contain an entry for each entry in clock-names. - clock-names : Must include the following entries: "nbclk" (L2/coherency fabric clock),
drivers/clocksource/time-armada-370-xp.c +28 -0
@@ -301,6 +301,34 @@ static void __init armada_xp_timer_init(struct device_node *np)CLOCKSOURCE_OF_DECLARE (armada_xp,"marvell,armada-xp-timer" , armada_xp_timer_init); +static void __init armada_375_timer_init (struct device_node *np) +{ +struct clk *clk; + + clk =of_clk_get_by_name (np,"fixed" ); +if (!IS_ERR (clk)) { +clk_prepare_enable (clk); + timer_clk =clk_get_rate (clk); + }else { + +/* +* This fallback is required in order to retain proper +* devicetree backwards compatibility. +*/ + clk =of_clk_get (np,0 ); + +/* Must have at least a clock */ +BUG_ON (IS_ERR (clk)); +clk_prepare_enable (clk); + timer_clk =clk_get_rate (clk) /TIMER_DIVIDER ; + timer25Mhz = false; + } + +armada_370_xp_timer_common_init (np); +} +CLOCKSOURCE_OF_DECLARE (armada_375,"marvell,armada-375-timer" , + armada_375_timer_init); +static void __init armada_370_timer_init (struct device_node *np) {struct clk *clk =of_clk_get (np,0 );
Signature · 1 line
1.9.1