mtd: spi-nor: support for SPI NOR deep power down

Incorporated the feedback regarding v1.

The reboot hook is necessary to reset the SPI NOR to a state where it's accessible by commands supported by all chips.
SoC's like i.mx6 have internal boot rom code which can read the actual bootloader from SPI NOR. The SoC doesn't know which SPI NOR is used and therefore can't use chip-specific commands.
Also the board design can't be blamed as lots of SPI NOR's don't have a reset pin.

A new DT property determines whether deep power down is used if supported by the chip. Default is not to use deep power down.
In addition to the DT property a new flag whether deep power down is supported is introduced to spi_nor_ids.
We dont' rely on the DT property only as DT might not care about the chip type and provide a generic chip name.
Not sure whether the majority of chips supports deep power down. Then it might be better to define the flag as "does not support DPD".

So far the flag is only set for chips I own devices with. Many more may support DPD.

---
 Documentation/devicetree/bindings/mtd/m25p80.txt |  5 ++
 drivers/mtd/spi-nor/spi-nor.c                    | 61 ++++++++++++++++++++----
 include/linux/mtd/spi-nor.h                      |  5 ++
 3 files changed, 63 insertions(+), 8 deletions(-)

index 4611aa8..0462d47 100644
@@ -16,6 +16,10 @@ Optional properties:
                    all chips and support for it can not be detected at runtime.
                    Refer to your chips' datasheet to check if this is supported
                    by your chip.
+- m25p,deep-power-down : Set chip to deep power down if idle. Opcodes for
+                         entering (0xb9) and leaving (0xab) deep power down mode
+                         are not supported by all chips. Property is ignored if
+                         chip doesn't support deep power down.
 
 Example:
 

@@ -26,4 +30,5 @@ Example:
 		reg = <0>;
 		spi-max-frequency = <40000000>;
 		m25p,fast-read;
+		m25p,deep-power-down;
 	};

index 4720b86..98616a9 100644
@@ -60,6 +60,9 @@
 #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
 #define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
 
+#define SPINOR_OP_DP		0xb9	/* deep power down */
+#define SPINOR_OP_RES		0xab	/* resume from deep power down */
+
 /* Status Register bits. */
 #define SR_WIP			1	/* Write in progress */
 #define SR_WEL			2	/* Write enable latch */

@@ -143,6 +146,7 @@ enum spi_nor_option_flags {
  * @flags:		flag options for the current SPI-NOR (SNOR_F_*)
  * @cfg:		used by the read_xfer/write_xfer
  * @cmd_buf:		used by the write_reg
+ * @deep_power_down:	deep power down mode supported and enabled
  * @prepare:		[OPTIONAL] do some preparations for the
  *			read/write/erase/lock/unlock operations
  * @unprepare:		[OPTIONAL] do some post work after the

@@ -172,6 +176,7 @@ struct spi_nor {
 	u32			flags;
 	struct spi_nor_xfer_cfg	cfg;
 	u8			cmd_buf[SPI_NOR_MAX_CMD_SIZE];
+	bool			deep_power_down;
 
 	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
 	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);

2.2.2