How can we support outer shareable on ARM64?
Hi,
Now, both cacheable memory shareability attribute and barrier are fixed to inner shareable. But I afraid some hardware need outer shareable. If hardware support both inner and outer, do we need to optimize?
for example(the code for now):
#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
#define smp_mb() dmb(ish)
How can we support both inner and outer shareable, or selectable?
Thanks
Zhen Lei
Quoted 2 lines · leizhen
Now, both cacheable memory shareability attribute and barrier are fixed to inner shareable.
That's correct for memory attributes. As for barriers, the mb() generates full system DSB.
Quoted 1 line
But I afraid some hardware need outer shareable.
Why? All processors or devices controlled by an operating system are expected to be in the same inner shareable domain (see shareable memory in B2.8.1 in the ARMv8 ARM).
Signature · 1 line
Catalin
Quoted 6 lines · Catalin Marinas
Quoted 2 lines · leizhen
Now, both cacheable memory shareability attribute and barrier are fixed to inner shareable.
That's correct for memory attributes. As for barriers, the
mb()generates full system DSB.
OK.
Quoted 7 lines
Quoted 2 lines
But I afraid some hardware need outer shareable.
Why? All processors or devices controlled by an operating system are expected to be in the same inner shareable domain (see shareable memory in B2.8.1 in the ARMv8 ARM).
OK. Thank you for help. I saw that sentence:
This architecture assumes that all PEs that use the same operating system or hypervisor are in the same Inner Shareable shareability domain.