: data pattern sensivity

Dear All,

I was looking inside Boris presentation at latest ELC (nice work!) and trying to understand a bit deeper the systematic data pattern problem. I also did some research on this ML, looking for some details about this topic, finding not so much more the original RFC thread:

http://thread.gmane.org/gmane.linux.drivers.devicetree/72230/

I search for this kind of information inside various MLC NAND datasheets that I've available on my desk but I cannot find any reference on this, maybe is called in a different way or maybe I'm looking to the wrong devices (e.g. I'm currently working with some Micron NANDs MT29F32G08CBADA, MT29F32G08CBACA..)

I CCed Boris and Jeff directly because maybe they can help me in better understanding the impact of this problem on some real device.

TIA & BR,

Andrea SCIAN

DAVE Embedded Systems

I'm always glad to help out. I'm not sure I quite understand the meaning of "data pattern sensivity", but when I read it seem related to ECC code word size and Cyclicdesign.com is a good resource and in particular http://cyclicdesign.com/whitepapers/Cyclic_Design_NAND_ECC.pdf. If I'm off track let me know and I will keep looking.

Jeff Lauruhn
NAND Application Engineer
Embedded Business Unit
Micron Technology, Inc

-----Original Message-----
From: Andrea Scian [mailto:[email protected]]
Sent: Friday, April 03, 2015 2:46 AM
To: mtd_mailinglist
Cc: Boris Brezillon; Jeff Lauruhn (jlauruhn)
Subject: [MLC NAND]: data pattern sensivity

Dear All,

I was looking inside Boris presentation at latest ELC (nice work!) and trying to understand a bit deeper the systematic data pattern problem. I also did some research on this ML, looking for some details about this topic, finding not so much more the original RFC thread:

http://thread.gmane.org/gmane.linux.drivers.devicetree/72230/

I search for this kind of information inside various MLC NAND datasheets that I've available on my desk but I cannot find any reference on this, maybe is called in a different way or maybe I'm looking to the wrong devices (e.g. I'm currently working with some Micron NANDs MT29F32G08CBADA, MT29F32G08CBACA..)

I CCed Boris and Jeff directly because maybe they can help me in better understanding the impact of this problem on some real device.

TIA & BR,

Andrea SCIAN

DAVE Embedded Systems

Il 03/04/2015 19:20, Jeff Lauruhn (jlauruhn) ha scritto:

Thanks for pointing out the whitepaper

I don't really know, but, IIUC, is something related to NAND technology and its impact is dependent from the specific MLC implementation. For sure Boris can help us in have a better understanding of this issue :-)

BR,

Andrea SCIAN

DAVE Embedded Systems

Hi,

I haven't read this paper yet, but according to the title I doubt it is related to the "repeated/systematic data pattern" issue.

Actually this problem was mentioned in the Micron document I pointed out in a previous thread ([1] page 14).
I also found a paper describing the benefit of data scrambling on MLC chips [2].

Best Regards,

Boris

[1]http://www.bswd.com/FMS09/FMS09-T2A-Grunzke.pdf [2]http://soc.yonsei.ac.kr/Abstract/International_journal/pdf/106_Data%20Randomization%20Scheme%20for%20Endurance%20Enhancement%20and%20Interference%20Mitigation%20of%20Multilevel%20Flash%20Memory%20Devices.pdf

Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Il 07/04/2015 13:19, Boris Brezillon ha scritto:

Thanks for linking this again.
I think that Jeff can help us in understanding this further. The documents is pretty old (2009) and is about TLC only. Does it mean that MLC are less (or not at all) affected by this issue?

This one is really interesting, thanks.
IIUC, what they say is that data scrambling is always useful in NAND flash to increase endurance (and also decrease RBER).
At the beginning I tough that it was a requirement of some specific NAND technology

BR,

Andrea SCIAN

DAVE Embedded Systems

Some MLC chips require a randomization step: take a look at this datasheet [1], page 21:
"Users are required to employ randomizer function in the NAND controller to meet target endurance of the device."

[1]http://www.100y.com.tw/pdf_file/37-SAMSUNG-K9GBG08U0A-SCB0.pdf

Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

I read back through the posts and I think we are talking about 2 separate things, random read time and randomization.

Rand Read (tR) assumes you are doing a single read of a page (worst case), but most data is stored in blocks sequentially, so data output can be improve significantly by read by taking advantage of commands like READ PAGE CACHE SEQUENTIAL which copies the next sequential page from the NAND Flash array to the data register.

Randomization is a relatively new feature, I'm no expert, but it's in general we know there are some distributions that are worse than others, and by randomizing the data we can avoid worst case and improve endurance.

Jeff Lauruhn
NAND Application Engineer
Embedded Business Unit
Micron Technology, Inc

-----Original Message-----
From: Boris Brezillon [mailto:[email protected]]
Sent: Tuesday, April 07, 2015 8:09 AM
To: Andrea Scian
Cc: Jeff Lauruhn (jlauruhn); mtd_mailinglist
Subject: Re: [MLC NAND]: data pattern sensivity

Some MLC chips require a randomization step: take a look at this datasheet [1], page 21:
"Users are required to employ randomizer function in the NAND controller to meet target endurance of the device."

[1]http://www.100y.com.tw/pdf_file/37-SAMSUNG-K9GBG08U0A-SCB0.pdf

--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Il 07/04/2015 19:45, Jeff Lauruhn (jlauruhn) ha scritto:

Definitely here I'm speaking about the latter.
By looking inside the datasheet (hynix, micron and so on) I have I've found no MLC part that explicitly required such a implementation, apart the one pointed out by Boris.

Kind Regards,

Andrea SCIAN

DAVE Embedded Systems

Andrea SCIAN

DAVE Embedded Systems