MIPS: initial infrastructure for Microchip PIC32 architecture.

PATCH Superseded Purna Chandra Mandal 2 participants 6 messages Dec 17, 2015 – Dec 22, 2015 MIPS

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Purna Chandra Mandal

author

2015-12-17 17:28 UTC #0 lore raw

PATCH 2/18 MIPS: initial infrastructure for Microchip PIC32 architecture.

Signed-off-by Purna Chandra Mandal <[email protected]>

---

 arch/mips/Kconfig                        |   5 ++
 arch/mips/Makefile                       |   1 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 +++++++
 arch/mips/include/asm/arch-pic32/pic32.h | 145 +++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/Kconfig             |  20 +++++
 arch/mips/mach-pic32/Makefile            |   7 ++
 arch/mips/mach-pic32/config.mk           |   8 ++
 arch/mips/mach-pic32/cpu.c               |  13 +++
 8 files changed, 230 insertions(+)
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/config.mk
 create mode 100644 arch/mips/mach-pic32/cpu.c

arch/mips/Kconfig +5 -0

index 7f7e258..2a707e2 100644
@@ -51,6 +51,10 @@ config TARGET_PB1X00
     select SUPPORTS_CPU_MIPS32_R2
     select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+config MACH_PIC32
+    bool "Support Microchip PIC32"
+    select OF_CONTROL
+    select DM
 
 endchoice

@@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS

arch/mips/Makefile +1 -0

index 43f0f5c..8b7c7e3 100644
@@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/

arch/mips/include/asm/arch-pic32/clock.h new file +31 -0

new file mode 100644
index 0000000..6a4270d
@@ -0,0 +1,31 @@
+/*
+ * (c) 2015 Purna Chandra Mandal purna.mandal at microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_CLOCK_H_
+#define __PIC32_CLOCK_H_
+
+/* clk */
+enum {
+    BASECLK,
+    PLLCLK,
+    MPLL,
+    SYSCLK,
+    PB1CLK,
+    PB2CLK,
+    PB3CLK,
+    PB4CLK,
+    PB5CLK,
+    PB6CLK,
+    PB7CLK,
+    REF1CLK,
+    REF2CLK,
+    REF3CLK,
+    REF4CLK,
+    REF5CLK,
+};
+
+#endif    /* __PIC32_CLOCK_H_ */

arch/mips/include/asm/arch-pic32/pic32.h new file +145 -0

145 lines not on this page · raw message

arch/mips/mach-pic32/Kconfig new file +20 -0

new file mode 100644
index 0000000..e4eaf5c
@@ -0,0 +1,20 @@
+menu "Microchip PIC32 platforms"
+    depends on MACH_PIC32
+
+config SYS_SOC
+    default "none"
+
+choice
+    prompt "PIC32 SoC select"
+
+endchoice
+
+choice
+    prompt "Board select"
+
+endchoice
+
+config PIC32_SUPPORTS_FDT_BOOT
+    bool "FDT Boot"
+
+endmenu

arch/mips/mach-pic32/Makefile new file +7 -0

new file mode 100644
index 0000000..cb42607
@@ -0,0 +1,7 @@
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.mandal at microchip.com.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y = cpu.o

arch/mips/mach-pic32/config.mk new file +8 -0

new file mode 100644
index 0000000..f17a3f4
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mtune=m14kec

arch/mips/mach-pic32/cpu.c new file +13 -0

new file mode 100644
index 0000000..58fd3ab
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+#include <common.h>
+
+phys_size_t initdram(int board_type)
+{
+    return 0;
+}

Signature · 1 line

1.8.3.1

Daniel Schwierzeck

2015-12-19 23:19 UTC #1 lore raw

PATCH 2/18 MIPS: initial infrastructure for Microchip PIC32 architecture.

Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:

Quoted 101 lines

Signed-off-by Purna Chandra Mandal <[email protected]>

---

 arch/mips/Kconfig                        |   5 ++
 arch/mips/Makefile                       |   1 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 +++++++
 arch/mips/include/asm/arch-pic32/pic32.h | 145 +++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/Kconfig             |  20 +++++
 arch/mips/mach-pic32/Makefile            |   7 ++
 arch/mips/mach-pic32/config.mk           |   8 ++
 arch/mips/mach-pic32/cpu.c               |  13 +++
 8 files changed, 230 insertions(+)
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/config.mk
 create mode 100644 arch/mips/mach-pic32/cpu.c

arch/mips/Kconfig +5 -0

index 7f7e258..2a707e2 100644
@@ -51,6 +51,10 @@ config TARGET_PB1X00
     select SUPPORTS_CPU_MIPS32_R2
     select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+config MACH_PIC32
+    bool "Support Microchip PIC32"
+    select OF_CONTROL
+    select DM
 
 endchoice

@@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS

arch/mips/Makefile +1 -0

index 43f0f5c..8b7c7e3 100644
@@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/

arch/mips/include/asm/arch-pic32/clock.h new file +31 -0

new file mode 100644
index 0000000..6a4270d
@@ -0,0 +1,31 @@
+/*
+ * (c) 2015 Purna Chandra Mandal purna.mandal at microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_CLOCK_H_
+#define __PIC32_CLOCK_H_
+
+/* clk */
+enum {
+    BASECLK,
+    PLLCLK,
+    MPLL,
+    SYSCLK,
+    PB1CLK,
+    PB2CLK,
+    PB3CLK,
+    PB4CLK,
+    PB5CLK,
+    PB6CLK,
+    PB7CLK,
+    REF1CLK,
+    REF2CLK,
+    REF3CLK,
+    REF4CLK,
+    REF5CLK,
+};
+
+#endif    /* __PIC32_CLOCK_H_ */

arch/mips/include/asm/arch-pic32/pic32.h new file +6 -0

new file mode 100644
index 0000000..4f2084f
@@ -0,0 +1,145 @@
+/*
+ * (c) 2015 Paul Thacker <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */

arch/mips/include/asm/arch-pic32/pic32.h line 16

Quoted 10 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +10 -0

+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#define _CLR_OFFSET    (0x4)
+#define _SET_OFFSET    (0x8)
+#define _INV_OFFSET    (0xc)
+
+/* System Configuration */
+#define PIC32_CFG_BASE(x) 0xbf800000

you should a base address as physical address as seen by the CPU (e.g. 0x1f800000). The driver then does a remap to KSEG1. But if you use device-tree, you should get base address and size of a register space from there. Example:

void __iomem *base = (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE)

arch/mips/include/asm/arch-pic32/pic32.h line 25

Quoted 9 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +9 -0

+#define CFGCON        (PIC32_CFG_BASE(x))
+#define DEVID        (PIC32_CFG_BASE(x) + 0x0020)
+#define SYSKEY        (PIC32_CFG_BASE(x) + 0x0030)
+#define PMD1        (PIC32_CFG_BASE(x) + 0x0040)
+#define PMD7        (PIC32_CFG_BASE(x) + 0x00a0)
+#define CFGEBIA        (PIC32_CFG_BASE(x) + 0x00c0)
+#define CFGEBIC        (PIC32_CFG_BASE(x) + 0x00d0)
+#define CFGPG        (PIC32_CFG_BASE(x) + 0x00e0)
+#define CFGMPLL        (PIC32_CFG_BASE(x) + 0x0100)

registers should only defined by their relative offset. The addition to the base address is not needed. A driver could do:

readl(base + CFGCON)

Quoted 165 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +120 -0

+
+/* Clock & Reset */
+#define RESET_BASE    0xbf800000
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE  (RESET_BASE + 0x0600)
+
+/* Reset Control Registers */
+#define RSWRST        (RESET_BASE + 0x1250)
+
+/* Oscillator Configuration */
+#define OSCCON        (RESET_BASE + 0x1200)
+#define SPLLCON        (RESET_BASE + 0x1220)
+#define REFO1CON    (RESET_BASE + 0x1280)
+#define REFO1TRIM    (RESET_BASE + 0x1290)
+#define PB1DIV        (RESET_BASE + 0x1340)
+
+/* Peripheral PORTA-PORTK / PORT0-PORT9 */
+enum {
+    PIC32_PORT_A = 0,
+    PIC32_PORT_B = 1,
+    PIC32_PORT_C = 2,
+    PIC32_PORT_D = 3,
+    PIC32_PORT_E = 4,
+    PIC32_PORT_F = 5,
+    PIC32_PORT_G = 6,
+    PIC32_PORT_H = 7,
+    PIC32_PORT_J = 8, /* no PORT_I */
+    PIC32_PORT_K = 9,
+    PIC32_PORT_MAX
+};
+
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE    0xbf800000
+#define U1RXR        (PPS_IN_BASE + 0x1468)
+#define U2RXR        (PPS_IN_BASE + 0x1470)
+#define SDI1R        (PPS_IN_BASE + 0x149c)
+#define SDI2R        (PPS_IN_BASE + 0x14a8)
+
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE    0xbf801500
+#define PPS_OUT(prt, pi)(PPS_OUT_BASE + ((((prt) * 16) + (pi)) << 2))
+#define RPA14R        PPS_OUT(PIC32_PORT_A, 14)
+#define RPB0R        PPS_OUT(PIC32_PORT_B, 0)
+#define RPB14R        PPS_OUT(PIC32_PORT_B, 14)
+#define RPD0R        PPS_OUT(PIC32_PORT_D, 0)
+#define RPD3R        PPS_OUT(PIC32_PORT_D, 3)
+#define RPG8R        PPS_OUT(PIC32_PORT_G, 8)
+#define RPG9R        PPS_OUT(PIC32_PORT_G, 9)
+
+/* Peripheral Pin Control */
+#define PINCTRL_BASE(x)    (0xbf860000 + (x * 0x0100))
+#define ANSEL(x)    (PINCTRL_BASE(x) + 0x00)
+#define ANSELCLR(x)    (ANSEL(x) + _CLR_OFFSET)
+#define ANSELSET(x)    (ANSEL(x) + _SET_OFFSET)
+#define TRIS(x)        (PINCTRL_BASE(x) + 0x10)
+#define TRISCLR(x)    (TRIS(x) + _CLR_OFFSET)
+#define TRISSET(x)    (TRIS(x) + _SET_OFFSET)
+#define PORT(x)        (PINCTRL_BASE(x) + 0x20)
+#define PORTCLR(x)    (PORT(x) + _CLR_OFFSET)
+#define PORTSET(x)    (PORT(x) + _SET_OFFSET)
+#define LAT(x)        (PINCTRL_BASE(x) + 0x30)
+#define LATCLR(x)    (LAT(x) + _CLR_OFFSET)
+#define LATSET(x)    (LAT(x) + _SET_OFFSET)
+#define ODC(x)        (PINCTRL_BASE(x) + 0x40)
+#define ODCCLR(x)    (ODC(x) + _CLR_OFFSET)
+#define ODCSET(x)    (ODC(x) + _SET_OFFSET)
+#define CNPU(x)        (PINCTRL_BASE(x) + 0x50)
+#define CNPUCLR(x)    (CNPU(x) + _CLR_OFFSET)
+#define CNPUSET(x)    (CNPU(x) + _SET_OFFSET)
+#define CNPD(x)        (PINCTRL_BASE(x) + 0x60)
+#define CNPDCLR(x)    (CNPD(x) + _CLR_OFFSET)
+#define CNPDSET(x)    (CNPD(x) + _SET_OFFSET)
+#define CNCON(x)    (PINCTRL_BASE(x) + 0x70)
+#define CNCONCLR(x)    (CNCON(x) + _CLR_OFFSET)
+#define CNCONSET(x)    (CNCON(x) + _SET_OFFSET)
+
+/* Get gpio# from peripheral port# and pin# */
+#define GPIO_PORT_PIN(_port, _pin) \
+        (((_port) << 4) + (_pin))
+
+/* USB Core */
+#define PIC32_USB_CORE_BASE    0xbf8e3000
+#define PIC32_USB_CTRL_BASE    0xbf884000
+
+/* SPI1-SPI6 */
+#define PIC32_SPI1_BASE        0xbf821000
+
+/* Prefetch Module */
+#define PREFETCH_BASE    0xbf8e0000
+#define PRECON        (PREFETCH_BASE)
+#define PRECONCLR    (PRECON + _CLR_OFFSET)
+#define PRECONSET    (PRECON + _SET_OFFSET)
+#define PRECONINV    (PRECON + _INV_OFFSET)
+
+#define PRESTAT        (PREFETCH_BASE + 0x0010)
+#define PRESTATCLR    (PRESTAT + _CLR_OFFSET)
+#define PRESTATSET    (PRESTAT + _SET_OFFSET)
+#define PRESTATINV    (PRESTAT + _INV_OFFSET)
+
+/* DDR2 Controller */
+#define PIC32_DDR2C_BASE    0xbf8e8000
+
+/* DDR2 PHY */
+#define PIC32_DDR2P_BASE    0xbf8e9100
+
+/* EBI */
+#define PIC32_EBI_BASE        0xbf8e1000
+
+/* SQI */
+#define PIC32_SQI_BASE        0xbf8e2000
+
+struct pic32_reg_atomic {
+    u32 raw;
+    u32 clr;
+    u32 set;
+    u32 inv;
+};
+
+#endif    /* __PIC32_REGS_H__ */

arch/mips/mach-pic32/Kconfig new file +20 -0

new file mode 100644
index 0000000..e4eaf5c
@@ -0,0 +1,20 @@
+menu "Microchip PIC32 platforms"
+    depends on MACH_PIC32
+
+config SYS_SOC
+    default "none"
+
+choice
+    prompt "PIC32 SoC select"
+
+endchoice
+
+choice
+    prompt "Board select"
+
+endchoice
+
+config PIC32_SUPPORTS_FDT_BOOT
+    bool "FDT Boot"
+
+endmenu

arch/mips/mach-pic32/Makefile new file +7 -0

new file mode 100644
index 0000000..cb42607
@@ -0,0 +1,7 @@
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.mandal at microchip.com.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y = cpu.o

arch/mips/mach-pic32/config.mk new file +0 -0

new file mode 100644
index 0000000..f17a3f4

arch/mips/mach-pic32/config.mk line 8

Quoted 8 lines

arch/mips/mach-pic32/config.mk new file +8 -0

@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mtune=m14kec

config.mk files are deprecated, so please do not create a new one. Such flags should be added with a cpuflags-$(xxx) line in arch/mips/config.mk

Quoted 20 lines

arch/mips/mach-pic32/cpu.c new file +13 -0

new file mode 100644
index 0000000..58fd3ab
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+#include <common.h>
+
+phys_size_t initdram(int board_type)
+{
+    return 0;
+}

Signature · 1 line

- Daniel

Purna Chandra Mandal

author

2015-12-21 12:49 UTC #2 lore raw

PATCH 2/18 MIPS: initial infrastructure for Microchip PIC32 architecture.

Quoted 117 lines · Daniel Schwierzeck

Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:

Quoted 100 lines

Signed-off-by Purna Chandra Mandal <[email protected]>

---

 arch/mips/Kconfig                        |   5 ++
 arch/mips/Makefile                       |   1 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 +++++++
 arch/mips/include/asm/arch-pic32/pic32.h | 145 +++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/Kconfig             |  20 +++++
 arch/mips/mach-pic32/Makefile            |   7 ++
 arch/mips/mach-pic32/config.mk           |   8 ++
 arch/mips/mach-pic32/cpu.c               |  13 +++
 8 files changed, 230 insertions(+)
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/config.mk
 create mode 100644 arch/mips/mach-pic32/cpu.c

arch/mips/Kconfig +5 -0

index 7f7e258..2a707e2 100644
@@ -51,6 +51,10 @@ config TARGET_PB1X00
     select SUPPORTS_CPU_MIPS32_R2
     select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+config MACH_PIC32
+    bool "Support Microchip PIC32"
+    select OF_CONTROL
+    select DM
 
 endchoice

@@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS

arch/mips/Makefile +1 -0

index 43f0f5c..8b7c7e3 100644
@@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/

arch/mips/include/asm/arch-pic32/clock.h new file +31 -0

new file mode 100644
index 0000000..6a4270d
@@ -0,0 +1,31 @@
+/*
+ * (c) 2015 Purna Chandra Mandal purna.mandal at microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_CLOCK_H_
+#define __PIC32_CLOCK_H_
+
+/* clk */
+enum {
+    BASECLK,
+    PLLCLK,
+    MPLL,
+    SYSCLK,
+    PB1CLK,
+    PB2CLK,
+    PB3CLK,
+    PB4CLK,
+    PB5CLK,
+    PB6CLK,
+    PB7CLK,
+    REF1CLK,
+    REF2CLK,
+    REF3CLK,
+    REF4CLK,
+    REF5CLK,
+};
+
+#endif    /* __PIC32_CLOCK_H_ */

arch/mips/include/asm/arch-pic32/pic32.h new file +6 -0

new file mode 100644
index 0000000..4f2084f
@@ -0,0 +1,145 @@
+/*
+ * (c) 2015 Paul Thacker <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */

arch/mips/include/asm/arch-pic32/pic32.h line 16

Quoted 10 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +10 -0

+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#define _CLR_OFFSET    (0x4)
+#define _SET_OFFSET    (0x8)
+#define _INV_OFFSET    (0xc)
+
+/* System Configuration */
+#define PIC32_CFG_BASE(x) 0xbf800000

Quoted 1 line

void __iomem *base = (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE)

ack. Will update.

Quoted 12 lines

arch/mips/include/asm/arch-pic32/pic32.h line 25

Quoted 9 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +9 -0

+#define CFGCON        (PIC32_CFG_BASE(x))
+#define DEVID        (PIC32_CFG_BASE(x) + 0x0020)
+#define SYSKEY        (PIC32_CFG_BASE(x) + 0x0030)
+#define PMD1        (PIC32_CFG_BASE(x) + 0x0040)
+#define PMD7        (PIC32_CFG_BASE(x) + 0x00a0)
+#define CFGEBIA        (PIC32_CFG_BASE(x) + 0x00c0)
+#define CFGEBIC        (PIC32_CFG_BASE(x) + 0x00d0)
+#define CFGPG        (PIC32_CFG_BASE(x) + 0x00e0)
+#define CFGMPLL        (PIC32_CFG_BASE(x) + 0x0100)

registers should only defined by their relative offset. The addition to the base address is not needed. A driver could do:

Quoted 1 line

readl(base + CFGCON)

ack.

Quoted 167 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +120 -0

+
+/* Clock & Reset */
+#define RESET_BASE    0xbf800000
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE  (RESET_BASE + 0x0600)
+
+/* Reset Control Registers */
+#define RSWRST        (RESET_BASE + 0x1250)
+
+/* Oscillator Configuration */
+#define OSCCON        (RESET_BASE + 0x1200)
+#define SPLLCON        (RESET_BASE + 0x1220)
+#define REFO1CON    (RESET_BASE + 0x1280)
+#define REFO1TRIM    (RESET_BASE + 0x1290)
+#define PB1DIV        (RESET_BASE + 0x1340)
+
+/* Peripheral PORTA-PORTK / PORT0-PORT9 */
+enum {
+    PIC32_PORT_A = 0,
+    PIC32_PORT_B = 1,
+    PIC32_PORT_C = 2,
+    PIC32_PORT_D = 3,
+    PIC32_PORT_E = 4,
+    PIC32_PORT_F = 5,
+    PIC32_PORT_G = 6,
+    PIC32_PORT_H = 7,
+    PIC32_PORT_J = 8, /* no PORT_I */
+    PIC32_PORT_K = 9,
+    PIC32_PORT_MAX
+};
+
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE    0xbf800000
+#define U1RXR        (PPS_IN_BASE + 0x1468)
+#define U2RXR        (PPS_IN_BASE + 0x1470)
+#define SDI1R        (PPS_IN_BASE + 0x149c)
+#define SDI2R        (PPS_IN_BASE + 0x14a8)
+
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE    0xbf801500
+#define PPS_OUT(prt, pi)(PPS_OUT_BASE + ((((prt) * 16) + (pi)) << 2))
+#define RPA14R        PPS_OUT(PIC32_PORT_A, 14)
+#define RPB0R        PPS_OUT(PIC32_PORT_B, 0)
+#define RPB14R        PPS_OUT(PIC32_PORT_B, 14)
+#define RPD0R        PPS_OUT(PIC32_PORT_D, 0)
+#define RPD3R        PPS_OUT(PIC32_PORT_D, 3)
+#define RPG8R        PPS_OUT(PIC32_PORT_G, 8)
+#define RPG9R        PPS_OUT(PIC32_PORT_G, 9)
+
+/* Peripheral Pin Control */
+#define PINCTRL_BASE(x)    (0xbf860000 + (x * 0x0100))
+#define ANSEL(x)    (PINCTRL_BASE(x) + 0x00)
+#define ANSELCLR(x)    (ANSEL(x) + _CLR_OFFSET)
+#define ANSELSET(x)    (ANSEL(x) + _SET_OFFSET)
+#define TRIS(x)        (PINCTRL_BASE(x) + 0x10)
+#define TRISCLR(x)    (TRIS(x) + _CLR_OFFSET)
+#define TRISSET(x)    (TRIS(x) + _SET_OFFSET)
+#define PORT(x)        (PINCTRL_BASE(x) + 0x20)
+#define PORTCLR(x)    (PORT(x) + _CLR_OFFSET)
+#define PORTSET(x)    (PORT(x) + _SET_OFFSET)
+#define LAT(x)        (PINCTRL_BASE(x) + 0x30)
+#define LATCLR(x)    (LAT(x) + _CLR_OFFSET)
+#define LATSET(x)    (LAT(x) + _SET_OFFSET)
+#define ODC(x)        (PINCTRL_BASE(x) + 0x40)
+#define ODCCLR(x)    (ODC(x) + _CLR_OFFSET)
+#define ODCSET(x)    (ODC(x) + _SET_OFFSET)
+#define CNPU(x)        (PINCTRL_BASE(x) + 0x50)
+#define CNPUCLR(x)    (CNPU(x) + _CLR_OFFSET)
+#define CNPUSET(x)    (CNPU(x) + _SET_OFFSET)
+#define CNPD(x)        (PINCTRL_BASE(x) + 0x60)
+#define CNPDCLR(x)    (CNPD(x) + _CLR_OFFSET)
+#define CNPDSET(x)    (CNPD(x) + _SET_OFFSET)
+#define CNCON(x)    (PINCTRL_BASE(x) + 0x70)
+#define CNCONCLR(x)    (CNCON(x) + _CLR_OFFSET)
+#define CNCONSET(x)    (CNCON(x) + _SET_OFFSET)
+
+/* Get gpio# from peripheral port# and pin# */
+#define GPIO_PORT_PIN(_port, _pin) \
+        (((_port) << 4) + (_pin))
+
+/* USB Core */
+#define PIC32_USB_CORE_BASE    0xbf8e3000
+#define PIC32_USB_CTRL_BASE    0xbf884000
+
+/* SPI1-SPI6 */
+#define PIC32_SPI1_BASE        0xbf821000
+
+/* Prefetch Module */
+#define PREFETCH_BASE    0xbf8e0000
+#define PRECON        (PREFETCH_BASE)
+#define PRECONCLR    (PRECON + _CLR_OFFSET)
+#define PRECONSET    (PRECON + _SET_OFFSET)
+#define PRECONINV    (PRECON + _INV_OFFSET)
+
+#define PRESTAT        (PREFETCH_BASE + 0x0010)
+#define PRESTATCLR    (PRESTAT + _CLR_OFFSET)
+#define PRESTATSET    (PRESTAT + _SET_OFFSET)
+#define PRESTATINV    (PRESTAT + _INV_OFFSET)
+
+/* DDR2 Controller */
+#define PIC32_DDR2C_BASE    0xbf8e8000
+
+/* DDR2 PHY */
+#define PIC32_DDR2P_BASE    0xbf8e9100
+
+/* EBI */
+#define PIC32_EBI_BASE        0xbf8e1000
+
+/* SQI */
+#define PIC32_SQI_BASE        0xbf8e2000
+
+struct pic32_reg_atomic {
+    u32 raw;
+    u32 clr;
+    u32 set;
+    u32 inv;
+};
+
+#endif    /* __PIC32_REGS_H__ */

arch/mips/mach-pic32/Kconfig new file +20 -0

new file mode 100644
index 0000000..e4eaf5c
@@ -0,0 +1,20 @@
+menu "Microchip PIC32 platforms"
+    depends on MACH_PIC32
+
+config SYS_SOC
+    default "none"
+
+choice
+    prompt "PIC32 SoC select"
+
+endchoice
+
+choice
+    prompt "Board select"
+
+endchoice
+
+config PIC32_SUPPORTS_FDT_BOOT
+    bool "FDT Boot"
+
+endmenu

arch/mips/mach-pic32/Makefile new file +7 -0

new file mode 100644
index 0000000..cb42607
@@ -0,0 +1,7 @@
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.mandal at microchip.com.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y = cpu.o

arch/mips/mach-pic32/config.mk new file +2 -0

new file mode 100644
index 0000000..f17a3f4
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2011

Quoted 8 lines

arch/mips/mach-pic32/config.mk line 8
Quoted 6 lines
arch/mips/mach-pic32/config.mk new file +6 -0
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mtune=m14kec
config.mk files are deprecated, so please do not create a new one. Such flags should be added with a cpuflags-$(xxx) line in arch/mips/config.mk

ack.

Quoted 20 lines

arch/mips/mach-pic32/cpu.c new file +13 -0

new file mode 100644
index 0000000..58fd3ab
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+#include <common.h>
+
+phys_size_t initdram(int board_type)
+{
+    return 0;
+}

Daniel Schwierzeck

2015-12-21 17:01 UTC #4 lore raw

PATCH 2/18 MIPS: initial infrastructure for Microchip PIC32 architecture.

In reply to Purna Chandra Mandal

Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:

Quoted 4 lines

Signed-off-by Purna Chandra Mandal <[email protected]>
---

Quoted 11 lines

 arch/mips/Kconfig                        |   5 ++
 arch/mips/Makefile                       |   1 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 +++++++
 arch/mips/include/asm/arch-pic32/pic32.h | 145 +++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/Kconfig             |  20 +++++
 arch/mips/mach-pic32/Makefile            |   7 ++
 arch/mips/mach-pic32/config.mk           |   8 ++
 arch/mips/mach-pic32/cpu.c               |  13 +++
 8 files changed, 230 insertions(+)
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h

I noticed in an other thread that CONFIG_ARCH_SYMLINKS is going to be deprecated. The preferred location for SoC specific header files is "arch/*/mach-*/include/mach/". A driver can then use "include <mach/file.h>".

I've already sent a patch for MIPS [1]. So please rebase to u-boot-mips/next and move those two files to arch/mips/mach-pic32/include/mach/.

Quoted 5 lines

 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/config.mk
 create mode 100644 arch/mips/mach-pic32/cpu.c

[1] http://patchwork.ozlabs.org/patch/559581/

Signature · 1 line

- Daniel

Purna Chandra Mandal

author

2015-12-22 13:38 UTC #3 lore raw

PATCH 2/18 MIPS: initial infrastructure for Microchip PIC32 architecture.

In reply to Daniel Schwierzeck

Quoted 117 lines · Daniel Schwierzeck

Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:

Quoted 100 lines

Signed-off-by Purna Chandra Mandal <[email protected]>

---

 arch/mips/Kconfig                        |   5 ++
 arch/mips/Makefile                       |   1 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 +++++++
 arch/mips/include/asm/arch-pic32/pic32.h | 145 +++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/Kconfig             |  20 +++++
 arch/mips/mach-pic32/Makefile            |   7 ++
 arch/mips/mach-pic32/config.mk           |   8 ++
 arch/mips/mach-pic32/cpu.c               |  13 +++
 8 files changed, 230 insertions(+)
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/config.mk
 create mode 100644 arch/mips/mach-pic32/cpu.c

arch/mips/Kconfig +5 -0

index 7f7e258..2a707e2 100644
@@ -51,6 +51,10 @@ config TARGET_PB1X00
     select SUPPORTS_CPU_MIPS32_R2
     select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+config MACH_PIC32
+    bool "Support Microchip PIC32"
+    select OF_CONTROL
+    select DM
 
 endchoice

@@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS

arch/mips/Makefile +1 -0

index 43f0f5c..8b7c7e3 100644
@@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/

arch/mips/include/asm/arch-pic32/clock.h new file +31 -0

new file mode 100644
index 0000000..6a4270d
@@ -0,0 +1,31 @@
+/*
+ * (c) 2015 Purna Chandra Mandal purna.mandal at microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_CLOCK_H_
+#define __PIC32_CLOCK_H_
+
+/* clk */
+enum {
+    BASECLK,
+    PLLCLK,
+    MPLL,
+    SYSCLK,
+    PB1CLK,
+    PB2CLK,
+    PB3CLK,
+    PB4CLK,
+    PB5CLK,
+    PB6CLK,
+    PB7CLK,
+    REF1CLK,
+    REF2CLK,
+    REF3CLK,
+    REF4CLK,
+    REF5CLK,
+};
+
+#endif    /* __PIC32_CLOCK_H_ */

arch/mips/include/asm/arch-pic32/pic32.h new file +6 -0

new file mode 100644
index 0000000..4f2084f
@@ -0,0 +1,145 @@
+/*
+ * (c) 2015 Paul Thacker <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */

arch/mips/include/asm/arch-pic32/pic32.h line 16

Quoted 10 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +10 -0

+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#define _CLR_OFFSET    (0x4)
+#define _SET_OFFSET    (0x8)
+#define _INV_OFFSET    (0xc)
+
+/* System Configuration */
+#define PIC32_CFG_BASE(x) 0xbf800000

Quoted 1 line

void __iomem *base = (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE)

ack. will update.

Quoted 12 lines

arch/mips/include/asm/arch-pic32/pic32.h line 25

Quoted 9 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +9 -0

+#define CFGCON        (PIC32_CFG_BASE(x))
+#define DEVID        (PIC32_CFG_BASE(x) + 0x0020)
+#define SYSKEY        (PIC32_CFG_BASE(x) + 0x0030)
+#define PMD1        (PIC32_CFG_BASE(x) + 0x0040)
+#define PMD7        (PIC32_CFG_BASE(x) + 0x00a0)
+#define CFGEBIA        (PIC32_CFG_BASE(x) + 0x00c0)
+#define CFGEBIC        (PIC32_CFG_BASE(x) + 0x00d0)
+#define CFGPG        (PIC32_CFG_BASE(x) + 0x00e0)
+#define CFGMPLL        (PIC32_CFG_BASE(x) + 0x0100)

registers should only defined by their relative offset. The addition to the base address is not needed. A driver could do:

Quoted 1 line

readl(base + CFGCON)

ack.

Quoted 167 lines

arch/mips/include/asm/arch-pic32/pic32.h new file +120 -0

+
+/* Clock & Reset */
+#define RESET_BASE    0xbf800000
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE  (RESET_BASE + 0x0600)
+
+/* Reset Control Registers */
+#define RSWRST        (RESET_BASE + 0x1250)
+
+/* Oscillator Configuration */
+#define OSCCON        (RESET_BASE + 0x1200)
+#define SPLLCON        (RESET_BASE + 0x1220)
+#define REFO1CON    (RESET_BASE + 0x1280)
+#define REFO1TRIM    (RESET_BASE + 0x1290)
+#define PB1DIV        (RESET_BASE + 0x1340)
+
+/* Peripheral PORTA-PORTK / PORT0-PORT9 */
+enum {
+    PIC32_PORT_A = 0,
+    PIC32_PORT_B = 1,
+    PIC32_PORT_C = 2,
+    PIC32_PORT_D = 3,
+    PIC32_PORT_E = 4,
+    PIC32_PORT_F = 5,
+    PIC32_PORT_G = 6,
+    PIC32_PORT_H = 7,
+    PIC32_PORT_J = 8, /* no PORT_I */
+    PIC32_PORT_K = 9,
+    PIC32_PORT_MAX
+};
+
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE    0xbf800000
+#define U1RXR        (PPS_IN_BASE + 0x1468)
+#define U2RXR        (PPS_IN_BASE + 0x1470)
+#define SDI1R        (PPS_IN_BASE + 0x149c)
+#define SDI2R        (PPS_IN_BASE + 0x14a8)
+
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE    0xbf801500
+#define PPS_OUT(prt, pi)(PPS_OUT_BASE + ((((prt) * 16) + (pi)) << 2))
+#define RPA14R        PPS_OUT(PIC32_PORT_A, 14)
+#define RPB0R        PPS_OUT(PIC32_PORT_B, 0)
+#define RPB14R        PPS_OUT(PIC32_PORT_B, 14)
+#define RPD0R        PPS_OUT(PIC32_PORT_D, 0)
+#define RPD3R        PPS_OUT(PIC32_PORT_D, 3)
+#define RPG8R        PPS_OUT(PIC32_PORT_G, 8)
+#define RPG9R        PPS_OUT(PIC32_PORT_G, 9)
+
+/* Peripheral Pin Control */
+#define PINCTRL_BASE(x)    (0xbf860000 + (x * 0x0100))
+#define ANSEL(x)    (PINCTRL_BASE(x) + 0x00)
+#define ANSELCLR(x)    (ANSEL(x) + _CLR_OFFSET)
+#define ANSELSET(x)    (ANSEL(x) + _SET_OFFSET)
+#define TRIS(x)        (PINCTRL_BASE(x) + 0x10)
+#define TRISCLR(x)    (TRIS(x) + _CLR_OFFSET)
+#define TRISSET(x)    (TRIS(x) + _SET_OFFSET)
+#define PORT(x)        (PINCTRL_BASE(x) + 0x20)
+#define PORTCLR(x)    (PORT(x) + _CLR_OFFSET)
+#define PORTSET(x)    (PORT(x) + _SET_OFFSET)
+#define LAT(x)        (PINCTRL_BASE(x) + 0x30)
+#define LATCLR(x)    (LAT(x) + _CLR_OFFSET)
+#define LATSET(x)    (LAT(x) + _SET_OFFSET)
+#define ODC(x)        (PINCTRL_BASE(x) + 0x40)
+#define ODCCLR(x)    (ODC(x) + _CLR_OFFSET)
+#define ODCSET(x)    (ODC(x) + _SET_OFFSET)
+#define CNPU(x)        (PINCTRL_BASE(x) + 0x50)
+#define CNPUCLR(x)    (CNPU(x) + _CLR_OFFSET)
+#define CNPUSET(x)    (CNPU(x) + _SET_OFFSET)
+#define CNPD(x)        (PINCTRL_BASE(x) + 0x60)
+#define CNPDCLR(x)    (CNPD(x) + _CLR_OFFSET)
+#define CNPDSET(x)    (CNPD(x) + _SET_OFFSET)
+#define CNCON(x)    (PINCTRL_BASE(x) + 0x70)
+#define CNCONCLR(x)    (CNCON(x) + _CLR_OFFSET)
+#define CNCONSET(x)    (CNCON(x) + _SET_OFFSET)
+
+/* Get gpio# from peripheral port# and pin# */
+#define GPIO_PORT_PIN(_port, _pin) \
+        (((_port) << 4) + (_pin))
+
+/* USB Core */
+#define PIC32_USB_CORE_BASE    0xbf8e3000
+#define PIC32_USB_CTRL_BASE    0xbf884000
+
+/* SPI1-SPI6 */
+#define PIC32_SPI1_BASE        0xbf821000
+
+/* Prefetch Module */
+#define PREFETCH_BASE    0xbf8e0000
+#define PRECON        (PREFETCH_BASE)
+#define PRECONCLR    (PRECON + _CLR_OFFSET)
+#define PRECONSET    (PRECON + _SET_OFFSET)
+#define PRECONINV    (PRECON + _INV_OFFSET)
+
+#define PRESTAT        (PREFETCH_BASE + 0x0010)
+#define PRESTATCLR    (PRESTAT + _CLR_OFFSET)
+#define PRESTATSET    (PRESTAT + _SET_OFFSET)
+#define PRESTATINV    (PRESTAT + _INV_OFFSET)
+
+/* DDR2 Controller */
+#define PIC32_DDR2C_BASE    0xbf8e8000
+
+/* DDR2 PHY */
+#define PIC32_DDR2P_BASE    0xbf8e9100
+
+/* EBI */
+#define PIC32_EBI_BASE        0xbf8e1000
+
+/* SQI */
+#define PIC32_SQI_BASE        0xbf8e2000
+
+struct pic32_reg_atomic {
+    u32 raw;
+    u32 clr;
+    u32 set;
+    u32 inv;
+};
+
+#endif    /* __PIC32_REGS_H__ */

arch/mips/mach-pic32/Kconfig new file +20 -0

new file mode 100644
index 0000000..e4eaf5c
@@ -0,0 +1,20 @@
+menu "Microchip PIC32 platforms"
+    depends on MACH_PIC32
+
+config SYS_SOC
+    default "none"
+
+choice
+    prompt "PIC32 SoC select"
+
+endchoice
+
+choice
+    prompt "Board select"
+
+endchoice
+
+config PIC32_SUPPORTS_FDT_BOOT
+    bool "FDT Boot"
+
+endmenu

arch/mips/mach-pic32/Makefile new file +7 -0

new file mode 100644
index 0000000..cb42607
@@ -0,0 +1,7 @@
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.mandal at microchip.com.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y = cpu.o

arch/mips/mach-pic32/config.mk new file +2 -0

new file mode 100644
index 0000000..f17a3f4
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2011

Quoted 8 lines

arch/mips/mach-pic32/config.mk line 8
Quoted 6 lines
arch/mips/mach-pic32/config.mk new file +6 -0
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mtune=m14kec
config.mk files are deprecated, so please do not create a new one. Such flags should be added with a cpuflags-$(xxx) line in arch/mips/config.mk

ack.

Quoted 20 lines

arch/mips/mach-pic32/cpu.c new file +13 -0

new file mode 100644
index 0000000..58fd3ab
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+#include <common.h>
+
+phys_size_t initdram(int board_type)
+{
+    return 0;
+}

Purna Chandra Mandal

author

2015-12-22 13:51 UTC #5 lore raw

PATCH 2/18 MIPS: initial infrastructure for Microchip PIC32 architecture.

In reply to Daniel Schwierzeck

Quoted 16 lines · Daniel Schwierzeck

Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:

Quoted 14 lines

Signed-off-by Purna Chandra Mandal <[email protected]>

---

 arch/mips/Kconfig                        |   5 ++
 arch/mips/Makefile                       |   1 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 +++++++
 arch/mips/include/asm/arch-pic32/pic32.h | 145 +++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/Kconfig             |  20 +++++
 arch/mips/mach-pic32/Makefile            |   7 ++
 arch/mips/mach-pic32/config.mk           |   8 ++
 arch/mips/mach-pic32/cpu.c               |  13 +++
 8 files changed, 230 insertions(+)
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h

Quoted 8 lines

I noticed in an other thread that CONFIG_ARCH_SYMLINKS is going to be deprecated. The preferred location for SoC specific header files is "arch/*/mach-*/include/mach/". A driver can then use "include <mach/file.h>".
I've already sent a patch for MIPS [1]. So please rebase to u-boot-mips/next and move those two files to arch/mips/mach-pic32/include/mach/.

Thanks. Will rebase and update accordingly.

Quoted 7 lines

Quoted 5 lines

 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/config.mk
 create mode 100644 arch/mips/mach-pic32/cpu.c

[1] http://patchwork.ozlabs.org/patch/559581/