parisc: add <asm/hash.h>
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PATCH v3 1/1 parisc: add <asm/hash.h>
PA-RISC is interesting; integer multiplies are implemented in the FPU, so are painful in the kernel. But it tries to be friendly to shift-and-add sequences.
__hash_32 is implemented using the same shift-and-add sequence as Microblaze, just scheduled for the PA7100. (It's 2-way superscalar but in-order, like the Pentium.)
hash_64 was tricky, but a suggestion from Jason Thong allowed a good solution by breaking up the multiplier. After an embarrassing amount of fiddling about, I found a 19-instruction sequence for the multiply that can be executed in 10 cycles using only 4 temporaries.
(The PA8xxx can issue 4 instructions per cycle, but 2 must be ALU ops and 2 must be loads/stores. And the final add can't be paired.)
An alternative implementation is included, but not enabled by default:
Thomas Wang's 64-to-32-bit hash. This is more compact than the multiply, but has a slightly longer dependency chain.
---
Okay, I'm happy with this one. Helge, could you test it whenever you get a chance?
I've left the alternate hash_64 path in for now, but the one not chosen should be deleted before sending to Linus.
arch/parisc/Kconfig | 1 + arch/parisc/include/asm/hash.h | 182 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 183 insertions(+) create mode 100644 arch/parisc/include/asm/hash.h
arch/parisc/Kconfig +1 -0
@@ -30,6 +30,7 @@ config PARISC select TTY # Needed for pdc_cons.c select HAVE_DEBUG_STACKOVERFLOW select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_HASH select HAVE_ARCH_SECCOMP_FILTER select ARCH_NO_COHERENT_DMA_MMAP
arch/parisc/include/asm/hash.h new file +182 -0
182 lines not on this page · raw message
Signature · 1 line
2.8.1
PATCH v4 1/1 parisc: add <asm/hash.h>
PA-RISC is interesting; integer multiplies are implemented in the FPU, so are painful in the kernel. But it tries to be friendly to shift-and-add sequences for constant multiplies.
__hash_32 is implemented using the same shift-and-add sequence as Microblaze, just scheduled for the PA7100. (It's 2-way superscalar but in-order, like the Pentium.)
hash_64 was tricky, but a suggestion from Jason Thong allowed a good solution by breaking up the multiplier. After a lot of manual optimization, I found a 19-instruction sequence for the multiply that can be executed in 10 cycles using only 4 temporaries.
(The PA8xxx can issue 4 instructions per cycle, but 2 must be ALU ops and 2 must be loads/stores. And the final add can't be paired.)
An alternative considered, but ultimately not used, was Thomas Wang's 64-to-32-bit integer hash. At 12 instructions, it's smaller, but they're all sequentially dependent, so it has longer latency.
https://web.archive.org/web/2011/http://www.concentric.net/~Ttwang/tech/inthash.htm
http://burtleburtle.net/bob/hash/integer.html
---
No functional change, just cleaned up a lot. This is final if no problems are found.
arch/parisc/Kconfig | 1 + arch/parisc/include/asm/hash.h | 146 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 147 insertions(+) create mode 100644 arch/parisc/include/asm/hash.h
arch/parisc/Kconfig +1 -0
@@ -30,6 +30,7 @@ config PARISC select TTY # Needed for pdc_cons.c select HAVE_DEBUG_STACKOVERFLOW select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_HASH select HAVE_ARCH_SECCOMP_FILTER select ARCH_NO_COHERENT_DMA_MMAP
arch/parisc/include/asm/hash.h new file +146 -0
146 lines not on this page · raw message
Signature · 1 line
2.8.1
Hi George,
Quoted 10 lines · George Spelvin
PA-RISC is interesting; integer multiplies are implemented in the FPU, so are painful in the kernel. But it tries to be friendly to shift-and-add sequences for constant multiplies.
=20__hash_32is implemented using the same shift-and-add sequence as Microblaze, just scheduled for the PA7100. (It's 2-way superscalar but in-order, like the Pentium.)
=20hash_64was tricky, but a suggestion from Jason Thong allowed a good solution by breaking up the multiplier. After a lot of manual
Quoted 8 lines
optimization, I found a 19-instruction sequence for the multiply that can be executed in 10 cycles using only 4 temporaries.
=20
(The PA8xxx can issue 4 instructions per cycle, but 2 must be ALU ops and 2 must be loads/stores. And the final add can't be paired.) =20
An alternative considered, but ultimately not used, was Thomas Wang's 64-to-32-bit integer hash. At 12 instructions, it's smaller, but the=
y're
Quoted 3 lines
all sequentially dependent, so it has longer latency. =20
https://web.archive.org/web/2011/http://www.concentric.net/~Ttwang/te=
ch/inthash.htm
Quoted 7 lines
http://burtleburtle.net/bob/hash/integer.html
=20Signed-off-by George Spelvin <[email protected]>Cc Helge Deller <[email protected]>---
No functional change, just cleaned up a lot. This is final if no pro=
blems
Quoted 1 line
are found.
Thanks, but two minor issues...
Quoted 2 lines
arch/parisc/Kconfig | 1 +
arch/parisc/include/asm/hash.h| 146 +++++++++++++++++++++++++++++++=
++++++++++
Quoted 8 lines
2 files changed, 147 insertions(+) create mode 100644 arch/parisc/include/asm/hash.h=20
arch/parisc/Kconfig +0
-0
arch/parisc/Kconfig config PARISC · line 35
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arch/parisc/Kconfig +1
-0@@ -30,6 +30,7 @@ config PARISC select TTY # Needed for pdc_cons.c select HAVE_DEBUG_STACKOVERFLOW select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_HASH select HAVE_ARCH_SECCOMP_FILTER select ARCH_NO_COHERENT_DMA_MMAP
Minor issue:
This line (ARCH_NO_COHERENT) is not yet in Linus' tree. I assume you diff'ed against -next or something?
Maybe you move the "select HAVE_ARCH_HASH" one or two lines up, or wait until the other patch went upstream?
arch/parisc/include/asm=
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arch/parisc/include/asm= renamed from arch/parisc/include/asm/hash.h +0
-0
/hash.h
Quoted 5 lines
new file mode 100644
index 00000000..fb992a3b
arch/parisc/include/asm/hash.h line 10
Quoted 10 lines
arch/parisc/include/asm/hash.h new file +10
-0@@ -0,0 +1,146 @@ +#ifndef _ASM_HASH_H +#define _ASM_HASH_H + +/* +* HP-PA only implements integer multiply in the FPU. However, for +* integer multiplies by constant, it has a number of shift-and-add +* (but no shift-and-subtract, sigh!) instructions that a compiler +* can synthesize a code sequence with. +* +* Unfortunately, GCC isn't very efficient at using them. For examp=
le
arch/parisc/include/asm/hash.h line 11
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* it uses three instructions for "x *=3D 21" when only two are need=
ed.
arch/parisc/include/asm/hash.h
Quoted 7 lines
arch/parisc/include/asm/hash.h new file +7
-0+* But we can find a sequence manually. +*/ + +#define HAVE_ARCH__HASH_32 1 + +/* +* This is a multiply by GOLDEN_RATIO_32 =3D 0x61C88647 optimized fo=
r the
arch/parisc/include/asm/hash.h line 19
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* PA7100 pairing rules. This is an in-order 2-way superscalar proc=
essor.
arch/parisc/include/asm/hash.h line 20
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* Only one instruction in a pair may be a shift (by more than 3 bit=
s),
arch/parisc/include/asm/hash.h line 21
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* but other than that, simple ALU ops (including shift-and-add by u=
p
arch/parisc/include/asm/hash.h
Quoted 6 lines
arch/parisc/include/asm/hash.h new file +6
-0+* to 3 bits) may be paired arbitrarily. +* +* PA8xxx processors also dual-issue ALU instructions, although with +* fewer constraints, so this schedule is good for them, too. +* +* This 6-step sequence was found by Yevgen Voronenko's implementati=
on
Quoted 17 lines
arch/parisc/include/asm/hash.h new file +17
-0+* of the Hcub algorithm at http://spiral.ece.cmu.edu/mcm/gen.html. +*/ +static inline u32 __attribute_const__ __hash_32(u32 x) +{ +u32 a, b, c; + +/* +* Phase 1: Compute a =3D (x << 19) + x, +* b =3D (x << 9) + a, c =3D (x << 23) + b. +*/ + a =3D x << 19; /* Two shifts can't be paired */ + b =3D x << 9; a +=3D x; + c =3D x << 23; b +=3D a; + c +=3D b; +/* Phase 2: Return (b<<11) + (c<<6) + (a<<3) - c */ + b <<=3D 11; + a +=3D c << 3; b -=3D c;
arch/parisc/include/asm/hash.h
Quoted 10 lines
arch/parisc/include/asm/hash.h new file +10
-0+return (a <<3 ) + b; +} + +#if BITS_PER_LONG =3D=3D 64 + +#define HAVE_ARCH_HASH_64 1 + +/* +* Finding a good shift-and-add chain for GOLDEN_RATIO_64 is tricky, +* because available software for the purpose chokes on constants th=
is
arch/parisc/include/asm/hash.h line 55
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* large. (It's mostly designed for compiling FIR filter coefficien=
ts
arch/parisc/include/asm/hash.h
Quoted 3 lines
arch/parisc/include/asm/hash.h new file +3
-0+* into FPGAs.) +* +* However, Jason Thong pointed out a work-around. The Hcub softwar=
e
arch/parisc/include/asm/hash.h line 59
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* (http://spiral.ece.cmu.edu/mcm/gen.html) is designed for *multipl=
e*
arch/parisc/include/asm/hash.h line 60
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* constant multiplication, and is good at finding shift-and-add cha=
ins
arch/parisc/include/asm/hash.h
Quoted 7 lines
arch/parisc/include/asm/hash.h new file +7
-0+* which share common terms. +* +* Looking at 0x0x61C8864680B583EB in binary: +* 0110000111001000100001100100011010000000101101011000001111101011 +* \______________/ \__________/ \_______/ \________/ +* \____________________________/ \____________________/ +* you can see the non-zero bits are divided into several well-separ=
ated
arch/parisc/include/asm/hash.h line 68
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arch/parisc/include/asm/hash.h new file +1
-0+* blocks. Hcub can find algorithms for those terms separately, whi=
ch
arch/parisc/include/asm/hash.h
Quoted 8 lines
arch/parisc/include/asm/hash.h new file +8
-0+* can then be shifted and added together. +* +* Dividing the input into 2, 3 or 4 blocks, Hcub can find solutions +* with 10, 9 or 8 adds, respectively, making a total of 11 for the +* whole number. +* +* Using just two large blocks, 0xC3910C8D << 31 in the high bits, +* and 0xB583EB in the low bits, produces as good an algorithm as an=
y,
arch/parisc/include/asm/hash.h
Quoted 3 lines
arch/parisc/include/asm/hash.h new file +3
-0+* and with one more small shift than alternatives. +* +* The high bits are a larger number and more work to compute, as we=
ll
arch/parisc/include/asm/hash.h line 81
Quoted 2 lines
arch/parisc/include/asm/hash.h new file +2
-0+* as needing one extra cycle to shift left 31 bits before the final +* addition, so they are the critical path for scheduling. The low =
bits
arch/parisc/include/asm/hash.h
Quoted 6 lines
arch/parisc/include/asm/hash.h new file +6
-0+* can fit into the scheduling slots left over. +*/ + + +/* +* This _ASSIGN(dst, src) macro performs "dst =3D src", but prevents=
GCC
arch/parisc/include/asm/hash.h
Quoted 4 lines
arch/parisc/include/asm/hash.h new file +4
-0+* from inferring anything about the value assigned to "dest". +* +* This prevents it from mis-optimizing certain sequences. +* In particular, gcc is annoyingly eager to combine consecutive shi=
fts.
arch/parisc/include/asm/hash.h line 92
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* Given "x <<=3D 19; y +=3D x; z +=3D x << 1;", GCC will turn this =
into
arch/parisc/include/asm/hash.h line 93
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* "y +=3D x << 19; z +=3D x << 20;" even though the latter sequence=
needs
arch/parisc/include/asm/hash.h
Quoted 4 lines
arch/parisc/include/asm/hash.h new file +4
-0+* an additional instruction and temporary register. +* +* Because no actual assembly code is generated, this construct is +* usefully portable across all GCC platforms, and so can be test-co=
mpiled
arch/parisc/include/asm/hash.h
Quoted 3 lines
arch/parisc/include/asm/hash.h new file +3
-0+* on non-PA systems. +* +* In two places, additional unused input dependencies are added. T=
his
arch/parisc/include/asm/hash.h line 101
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* forces GCC's scheduling so it does not rearrange instructions too=
much.
arch/parisc/include/asm/hash.h line 102
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+* Because the PA-8xxx is out of order, I'm not sure how much this m=
atters,
arch/parisc/include/asm/hash.h
Quoted 3 lines
arch/parisc/include/asm/hash.h new file +3
-0+* but why make it more difficult for the processor than necessary? +*/ +#define _ASSIGN (dst, src, ...) asm("" : "=3Dr" (dst) : "0" (src), ##=
__VA_ARGS__)
arch/parisc/include/asm/hash.h
Quoted 3 lines
arch/parisc/include/asm/hash.h new file +3
-0+ +/* +* Multiply by GOLDEN_RATIO_64 =3D 0x0x61C8864680B583EB using a heav=
ily
Quoted 19 lines
arch/parisc/include/asm/hash.h new file +19
-0+* optimized shift-and-add sequence. +* +* Without the final shift, the multiply proper is 19 instructions, +* 10 cycles and uses only 4 temporaries. Whew! +* +* You are not expected to understand this. +*/ +static __always_inline u32 __attribute_const__ +hash_64 (u64 a,unsigned int bits) +{ +u64 b, c, d; + +/* +* Encourage GCC to move a dynamic shift to %sar early, +* thereby freeing up an additional temporary register. +*/ +if (!__builtin_constant_p (bits)) + asm("" :"=3Dq" (bits) :"0" (64 - bits)); +else
arch/parisc/include/asm/hash.h
Quoted 10 lines
arch/parisc/include/asm/hash.h new file +10
-0+ bits =3D 64 - bits; + + _ASSIGN(b, a*5); c =3D a << 13; + b =3D (b <<2 ) + a;_ASSIGN (d, a <<17 ); + a =3D b + (a << 1); c +=3D d; + d =3D a << 10; _ASSIGN(a, a << 19); + d =3D a - d; _ASSIGN(a, a << 4, "X" (d)); + c +=3D b; a +=3D b; + d -=3D c; c +=3D a << 1; + a +=3D c << 3; _ASSIGN(b, b << 7+31, "X" (c), "X" (d));
This line produces compiler warnings:arch/parisc/include/asm/hash.h: In function =91hash_64=92:arch/parisc/include/asm/hash.h:137:29: warning: suggest parentheses aro= und =91+=92 inside =91<<=92 [-Wparentheses]
a +=3D c << 3; _ASSIGN(b, b << 7+31, "X" (c), "X" (d));
^You should add () around 7+31.
With those changes I sucessfully tested it on a 64bit parisc kernel.
So, please add
THANKS!
Helge
arch/parisc/include/asm/hash.h line 142
Quoted 5 lines
arch/parisc/include/asm/hash.h new file +5
-0+ a <<=3D 31; b +=3D d; + a +=3D b; +return a >> bits; +} +#undef _ASSIGN/* We're a widely-used header file, so don't litter! =
*/
Quoted 5 lines
arch/parisc/include/asm/hash.h new file +4
-0+ +#endif /* BITS_PER_LONG =3D=3D 64 */ + +#endif /* _ASM_HASH_H */ =20
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Quoted 5 lines · Helge Deller
Minor issue:
This line (ARCH_NO_COHERENT) is not yet in Linus' tree. I assume you diff'ed against -next or something?
Maybe you move the "selectHAVE_ARCH_HASH" one or two lines up, or wait until the other patch went upstream?
No, I'm working against v4.6, and the line is there. Line 34 of "git show v4.6:arch/parisc/Kconfig".
You pulled my git tree, so you can see what I'm working on top of.
Quoted 3 lines
arch/parisc/include/asm/hash.h line 137
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+ a += c <<3 ;_ASSIGN (b, b <<7 +31 ,"X" (c),"X" (d));This line produces compiler warnings:
Thanks for catching that.
Quoted 2 lines
So, please add
Acked-by Helge Deller <[email protected]>
Done and pushed out to git://ftp.sciencehorizons.net/linux.git hash
Would you like to take it via the PA-RISC tree? I don't think a "performance fix" like this is 4.7-rc material (I think it's low-risk, so I don't object, but I think Linus would) so it has to wait for 4.8 either way.
Quoted 1 line
THANKS!
You're very welcome. I really wanted to improve it for *every* platform, so thank you for your help. I still haven't heard from the Microblaze guys.
Getting it down to 10 cycles was a fun micro-optimization challenge. I'm just annoyed I wasted to much time optimizing for a misunderstanding of the PA-8800 pipeline. The large print ("QUAD-ISSUE!") giveth, and the small print taketh waway.
Helge Deller
maintainerQuoted 5 lines · George Spelvin
Quoted 3 lines · Helge Deller
arch/parisc/include/asm/hash.h line 137
Quoted 1 line
arch/parisc/include/asm/hash.h new file +1
-0+ a += c <<3 ;_ASSIGN (b, b <<7 +31 ,"X" (c),"X" (d));This line produces compiler warnings:
Quoted 8 lines
Thanks for catching that.
Quoted 2 lines
So, please add
Acked-by Helge Deller <[email protected]>Done and pushed out to
git://ftp.sciencehorizons.net/linux.githashWould you like to take it via the PA-RISC tree?
Yes, I will take it through the parisc tree.
Helge