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Question on Enabling hypervisor mode in u-boot

U-Boot Keerthy 3 participants 8 messages Aug 1, 2016 – Aug 4, 2016

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Keerthy

author

2016-08-01 10:07 UTC #0 lore raw

Hi Alexander,

I am trying to enable hypervisor in u-boot for DRA7(A15 based) family of SoCs which does not have LPAE support yet.

Is it mandatory for LPAE to be enabled before enabling hypervisor for A15?

I was looking at commit:

commit d990f5c834f1b42293fb53e4fd7f3aa988184196

Author: Alexander Graf <[email protected]>
Date:   Wed Mar 16 15:41:21 2016 +0100

arm: Add support for HYP mode and LPAE page tables

and the is_hyp always returns 0 when LPAE config option is not enabled.

Just wanted to confirm if that is mandatory.

Best Regards,
Keerthy

Andreas Färber

2016-08-01 17:41 UTC #1 lore raw

Hi Keerthy,

Am 01.08.2016 um 12:07 schrieb Keerthy:

Quoted 4 lines

I am trying to enable hypervisor in u-boot for DRA7(A15 based) family of SoCs which does not have LPAE support yet.
Is it mandatory for LPAE to be enabled before enabling hypervisor for A15?

On the Linux kernel side you can't enable KVM without LPAE. I assume the same will hold true in U-Boot then.

Regards,
Andreas

Signature · 3 lines

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Keerthy

author

2016-08-02 02:19 UTC #2 lore raw

Quoted 10 lines · Andreas F?rber

Hi Keerthy,
Am 01.08.2016 um 12:07 schrieb Keerthy:
Quoted 4 lines
I am trying to enable hypervisor in u-boot for DRA7(A15 based) family of SoCs which does not have LPAE support yet.
Is it mandatory for LPAE to be enabled before enabling hypervisor for A15?
On the Linux kernel side you can't enable KVM without LPAE. I assume the same will hold true in U-Boot then.

Hi Andreas,

Okay. Thanks for the confirmations. I will try with LPAE config defined in u-boot also.

Best Regards,
Keerthy

Quoted 4 lines

Regards,
Andreas

Alexander Graf

2016-08-01 21:46 UTC #3 lore raw

In reply to Keerthy

Quoted 8 lines · Keerthy

Hi Alexander,
I am trying to enable hypervisor in u-boot for DRA7(A15 based) family of SoCs which does not have LPAE support yet.
Is it mandatory for LPAE to be enabled before enabling hypervisor for A15?

HYP mode shares the same page table layout as the LPAE one. I?m actually surprised you managed to configure an A15 without LPAE. Are you sure it doesn?t support it?

Alex

Keerthy

author

2016-08-02 01:54 UTC #4 lore raw

Quoted 10 lines · Alexander Graf

Quoted 8 lines · Keerthy
Hi Alexander,
I am trying to enable hypervisor in u-boot for DRA7(A15 based) family of SoCs which does not have LPAE support yet.
Is it mandatory for LPAE to be enabled before enabling hypervisor for A15?
HYP mode shares the same page table layout as the LPAE one. I?m actually surprised you managed to configure an A15 without LPAE. Are you sure it doesn?t support it?

I meant CONFIG_LPAE not enabled yet in our defconfig. I was trying to get hyp mode enabled and saw that enabling LPAE config seemed mandatory as per your commit.

Quoted 4 lines

Alex

Keerthy

author

2016-08-02 11:59 UTC #5 lore raw

Hi Alex,

Quoted 14 lines · Keerthy

Quoted 11 lines · Alexander Graf
Quoted 10 lines · Keerthy
Hi Alexander,
I am trying to enable hypervisor in u-boot for DRA7(A15 based) family of SoCs which does not have LPAE support yet.
Is it mandatory for LPAE to be enabled before enabling hypervisor for A15?

Quoted 7 lines

Quoted 3 lines
HYP mode shares the same page table layout as the LPAE one. I?m actually surprised you managed to configure an A15 without LPAE. Are you sure it doesn?t support it?
I meant CONFIG_LPAE not enabled yet in our defconfig. I was trying to get hyp mode enabled and saw that enabling LPAE config seemed mandatory as per your commit.

I am referring
http://liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf.

Attrm[3:0] bits for DCACHE_WRITEALLOC, DCACHE_WRITEBACK, DCACHE_WRITETHROUGH definitions.

DCACHE_WRITEBACK should have 0x3 << 2 to get 11RW for MAIRn.Attrm[3:0] encoding.

Correct me if i am wrong of referring a wrong document.

Regards,
Keerthy

Quoted 9 lines

Quoted 5 lines
Alex
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Alexander Graf

2016-08-04 05:21 UTC #6 lore raw

Quoted 29 lines · Keerthy

Hi Alex,
Quoted 14 lines · Keerthy
Quoted 11 lines · Alexander Graf
Quoted 10 lines · Keerthy
Hi Alexander,
I am trying to enable hypervisor in u-boot for DRA7(A15 based) family of SoCs which does not have LPAE support yet.
Is it mandatory for LPAE to be enabled before enabling hypervisor for A15?
Quoted 7 lines
Quoted 3 lines
HYP mode shares the same page table layout as the LPAE one. I?m actually surprised you managed to configure an A15 without LPAE. Are you sure it doesn?t support it?
I meant CONFIG_LPAE not enabled yet in our defconfig. I was trying to get hyp mode enabled and saw that enabling LPAE config seemed mandatory as per your commit.

Quoted 7 lines

I am referring http://liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf.
Attrm[3:0] bits for DCACHE_WRITEALLOC, DCACHE_WRITEBACK, DCACHE_WRITETHROUGH definitions.
DCACHE_WRITEBACK should have 0x3 << 2 to get 11RW for MAIRn.Attrm[3:0] encoding.
Correct me if i am wrong of referring a wrong document.

I?m not quite sure I understand your issue correctly. If you want to run in HYP mode, the only page table format available is the ?long-descriptor? page table format, which is the same as the LPAE page table format. That?s the one that also puts the caching modes into MAIR registers instead of the PTEs.

So if you want to enable page tables (which you need to enable in order to enable caching), you have to write page tables in the LPAE format if you?re running in HYP mode. That?s why the config option is mandatory.

See sections B3.1.3 and B3.3 in the document you linked to:

"the translation tables for the Non-secure PL2 stage 1 translations, and for the Non-secure PL1&0 stage 2 translations, must use the Long-descriptor translation table format."

Alex

Keerthy

author

2016-08-04 05:30 UTC #7 lore raw

Quoted 37 lines · Alexander Graf

Quoted 29 lines · Keerthy
Hi Alex,
Quoted 14 lines · Keerthy
Quoted 11 lines · Alexander Graf
Quoted 10 lines · Keerthy
Hi Alexander,
I am trying to enable hypervisor in u-boot for DRA7(A15 based) family of SoCs which does not have LPAE support yet.
Is it mandatory for LPAE to be enabled before enabling hypervisor for A15?
Quoted 7 lines
Quoted 3 lines
HYP mode shares the same page table layout as the LPAE one. I?m actually surprised you managed to configure an A15 without LPAE. Are you sure it doesn?t support it?
I meant CONFIG_LPAE not enabled yet in our defconfig. I was trying to get hyp mode enabled and saw that enabling LPAE config seemed mandatory as per your commit.
Quoted 7 lines
I am referring http://liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf.
Attrm[3:0] bits for DCACHE_WRITEALLOC, DCACHE_WRITEBACK, DCACHE_WRITETHROUGH definitions.
DCACHE_WRITEBACK should have 0x3 << 2 to get 11RW for MAIRn.Attrm[3:0] encoding.
Correct me if i am wrong of referring a wrong document.

Quoted 7 lines

I?m not quite sure I understand your issue correctly. If you want to run in HYP mode, the only page table format available is the ?long-descriptor? page table format, which is the same as the LPAE page table format. That?s the one that also puts the caching modes into MAIR registers instead of the PTEs.
So if you want to enable page tables (which you need to enable in order to enable caching), you have to write page tables in the LPAE format if you?re running in HYP mode. That?s why the config option is mandatory.
See sections B3.1.3 and B3.3 in the document you linked to:
"the translation tables for the Non-secure PL2 stage 1 translations, and for the Non-secure PL1&0 stage 2 translations, must use the Long-descriptor translation table format."

Thanks for the confirmations and pointers. I will go through that part of ARM documentation.

Best Regards,
Keerthy

Quoted 4 lines

Alex