drm/msm/dpu: add support for clk and bw scaling for display

PATCH [email protected] 2 participants 2 messages Nov 24, 2020

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2020-11-24 12:57 UTC #0 lore raw

Quoted 37 lines · Amit Pundir

Quoted 9 lines · Rob Clark
Quoted 7 lines · Kalyan Thota
This change adds support to scale src clk and bandwidth as per composition requirements.
Interconnect registration for bw has been moved to mdp device node from mdss to facilitate the scaling.
Quoted 7 lines
Quoted 4 lines
Changes in v1:
- Address armv7 compilation issues with the patch (Rob)
Signed-off-by Kalyan Thota <[email protected]>
Reviewed-by Rob Clark <[email protected]>
Hi Kalyan, Rob,
This patch broke the display on the PocoF1 phone (sdm845-xiaomi-beryllium.dts) running AOSP.
I can boot to UI but the display is frozen soon after that and dmesg is full of following errors:
[drm:dpu_core_perf_crtc_update:397] [dpu error]crtc-65: failed to update bus bw vote
[drm:dpu_core_perf_crtc_check:203] [dpu error]exceeds bandwidth:
7649746kb > 6800000kb
[drm:dpu_crtc_atomic_check:969] [dpu error]crtc65 failed performance check -7 [drm:dpu_core_perf_crtc_check:203] [dpu error]exceeds bandwidth:
7649746kb > 6800000kb
[drm:dpu_crtc_atomic_check:969] [dpu error]crtc65 failed performance check -7 [drm:dpu_core_perf_crtc_check:203] [dpu error]exceeds bandwidth:
7649746kb > 6800000kb
[drm:dpu_crtc_atomic_check:969] [dpu error]crtc65 failed performance check -7

Quoted 8 lines

Here is the full dmesg https://pastebin.ubuntu.com/p/PcSdNgMnYw/.
Georgi pointed out following patch but it didn't help,
https://lore.kernel.org/dri-devel/[email protected]/
Am I missing any other followup fix?
Regards,
Amit Pundir
__

Hi Amit,

Apologies for the delay.

I have gone through the logs and referred to the below panel file for the timings.
https://github.com/Matheus-Garbelini/Kernel-Sphinx-Pocophone-F1/blob/master/arch/arm64/boot/dts/qcom/dsi-panel-tianma-fhd-nt36672a-video.dtsi

if the above is correct file, then below could be the possible root cause.

The panel back porch and pw is less and it is causing the prefill bw requirement to shoot up per layer as currently we are not considering front porch in the calculation. can you please try the attached patch in the email as a solution and provide me the feedback, i'll post it as a formal change.

Thanks,
Kalyan

_____________________________________________

Quoted 3 lines

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From 028fb47ccc5a3f8f8e51513bd2719aa14c68ac09 Mon Sep 17 00:00:00 2001
From: Kalyan Thota <[email protected]>
Date: Tue, 24 Nov 2020 02:39:52 -0800
Subject: [PATCH] drm: msm: dpu: consider front porch in the prefill
calculation

In case of panels with low vertical back porch and pw, the prefill bw will increase as we will have less time to fetch and fill all the hw latency buffers.

for ex: hw_latnecy_lines = 24, and if vbp+pw = 10 then we need to fetch 24 lines of data in 10 line times. This will increase prefill bw requirement.

DPU hw can fetch data during front porch also provided prefetch is enabled. Use front porch also into the prefill caluculation as driver enables prefetch if the blanking is not sufficient to fill the latency lines.

Signed-off-by Kalyan Thota <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +9 -2

index 7ea90d2..315b999 100644
@@ -151,7 +151,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
 	u64 plane_bw;
 	u32 hw_latency_lines;
 	u64 scale_factor;
-	int vbp, vpw;
+	int vbp, vpw, vfp;
 
 	pstate = to_dpu_plane_state(plane->state);
 	mode = &plane->state->crtc->mode;

@@ -164,6 +164,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
 	fps = drm_mode_vrefresh(mode);
 	vbp = mode->vtotal - mode->vsync_end;
 	vpw = mode->vsync_end - mode->vsync_start;
+	vfp = mode->vsync_start - mode->vdisplay;
 	hw_latency_lines =  dpu_kms->catalog->perf.min_prefill_lines;
 	scale_factor = src_height > dst_height ?
 		mult_frac(src_height, 1, dst_height) : 1;

@@ -176,7 +177,13 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
 		src_width * hw_latency_lines * fps * fmt->bpp *
 		scale_factor * mode->vtotal;
 
-	do_div(plane_prefill_bw, (vbp+vpw));
+	if ((vbp+vpw) > hw_latency_lines)
+		do_div(plane_prefill_bw, (vbp+vpw));
+	else if ((vbp+vpw+vfp) < hw_latency_lines)
+		do_div(plane_prefill_bw, (vbp+vpw+vfp));
+	else
+		do_div(plane_prefill_bw, hw_latency_lines);
+
 
 	pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
 }

Signature · 1 line

2.7.4

Amit Pundir

2020-11-24 15:56 UTC #1 lore raw

Hi Kalyan,

Quoted 48 lines · On Tue, 24 Nov 2020 at 18:27, <[email protected]> wrote:

Quoted 46 lines · Amit Pundir
Quoted 10 lines · Rob Clark
Quoted 7 lines · Kalyan Thota
This change adds support to scale src clk and bandwidth as per composition requirements.
Interconnect registration for bw has been moved to mdp device node from mdss to facilitate the scaling.
Quoted 7 lines
Quoted 4 lines
Changes in v1:
- Address armv7 compilation issues with the patch (Rob)
Signed-off-by Kalyan Thota <[email protected]>
Reviewed-by Rob Clark <[email protected]>
Hi Kalyan, Rob,
This patch broke the display on the PocoF1 phone (sdm845-xiaomi-beryllium.dts) running AOSP.
I can boot to UI but the display is frozen soon after that and dmesg is full of following errors:
[drm:dpu_core_perf_crtc_update:397] [dpu error]crtc-65: failed to update bus bw vote
[drm:dpu_core_perf_crtc_check:203] [dpu error]exceeds bandwidth:
7649746kb > 6800000kb
[drm:dpu_crtc_atomic_check:969] [dpu error]crtc65 failed performance check -7
[drm:dpu_core_perf_crtc_check:203] [dpu error]exceeds bandwidth:
7649746kb > 6800000kb
[drm:dpu_crtc_atomic_check:969] [dpu error]crtc65 failed performance check -7
[drm:dpu_core_perf_crtc_check:203] [dpu error]exceeds bandwidth:
7649746kb > 6800000kb
[drm:dpu_crtc_atomic_check:969] [dpu error]crtc65 failed performance check -7
Here is the full dmesg https://pastebin.ubuntu.com/p/PcSdNgMnYw/.
Georgi pointed out following patch but it didn't help,
https://lore.kernel.org/dri-devel/[email protected]/
Am I missing any other followup fix?

Quoted 7 lines

Quoted 3 lines
Regards,
Amit Pundir
__
Hi Amit,
Apologies for the delay.

No worries at all.

Quoted 5 lines

I have gone through the logs and referred to the below panel file for the timings.
https://github.com/Matheus-Garbelini/Kernel-Sphinx-Pocophone-F1/blob/master/arch/arm64/boot/dts/qcom/dsi-panel-tianma-fhd-nt36672a-video.dtsi

Quoted 8 lines

if the above is correct file, then below could be the possible root cause.
The panel back porch and pw is less and it is causing the prefill bw requirement to shoot up per layer as currently we are not considering front porch in the calculation. can you please try the attached patch in the email as a solution and provide me the feedback, i'll post it as a formal change.

The attached patch worked for me. Thanks a lot for looking closely into this issue.

Regards,
Amit Pundir

Quoted 8 lines

Thanks,
Kalyan
_____________________________________________
Quoted 3 lines
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno