drm: meson: global clean-up (use proper macros, update comments ...)
cover drm: meson: global clean-up (use proper macros, update comments ...)
This patch series aims to clean-up differents parts of the drm meson code source.
Couple macros have been defined and used to set several registers instead of using magic constants.
I also took the opportunity to:
- add/remove/update comments
- remove useless code
- minor fix/improvment
Julien Masson (9):
drm: meson: mask value when writing bits relaxed
drm: meson: crtc: use proper macros instead of magic constants
drm: meson: drv: use macro when initializing vpu
drm: meson: vpp: use proper macros instead of magic constants
drm: meson: viu: use proper macros instead of magic constants
drm: meson: venc: use proper macros instead of magic constants
drm: meson: global clean-up
drm: meson: add macro used to enable HDMI PLL
drm: meson: venc: set the correct macrovision max amplitude value
drivers/gpu/drm/meson/meson_crtc.c | 17 ++- drivers/gpu/drm/meson/meson_drv.c | 26 +++- drivers/gpu/drm/meson/meson_dw_hdmi.c | 2 + drivers/gpu/drm/meson/meson_dw_hdmi.h | 12 +- drivers/gpu/drm/meson/meson_plane.c | 2 +- drivers/gpu/drm/meson/meson_registers.h | 136 ++++++++++++++++--- drivers/gpu/drm/meson/meson_vclk.c | 7 +- drivers/gpu/drm/meson/meson_venc.c | 169 ++++++++++++++++++------ drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- drivers/gpu/drm/meson/meson_viu.c | 82 ++++++------ drivers/gpu/drm/meson/meson_vpp.c | 27 ++-- 11 files changed, 362 insertions(+), 121 deletions(-)
Signature · 1 line
2.17.1
PATCH 1/9 drm: meson: mask value when writing bits relaxed
The value used in the macro writel_bits_relaxed has to be masked since we don't want change the bits outside the mask.
--- drivers/gpu/drm/meson/meson_registers.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/meson/meson_registers.h +1 -1
@@ -20,7 +20,7 @@#define _REG (reg) ((reg) << 2)#define writel_bits_relaxed (mask, val, addr) \ - writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) + writel_relaxed((readl_relaxed(addr) & ~(mask)) | ((val) & (mask)), addr)/* vpp2 */ #define VPP2_DUMMY_DATA 0x1900
Signature · 1 line
2.17.1
PATCH 2/9 drm: meson: crtc: use proper macros instead of magic constants
In reply to Julien MassonThis patch add new macros which describe couple bits field of the following registers:
- VD1_BLEND_SRC_CTRL
- VPP_SC_MISC
--- drivers/gpu/drm/meson/meson_crtc.c | 17 +++++++++++------ drivers/gpu/drm/meson/meson_registers.h | 16 ++++++++++++++++ 2 files changed, 27 insertions(+), 6 deletions(-)
drivers/gpu/drm/meson/meson_crtc.c +11 -6
@@ -267,11 +267,11 @@ static void meson_crtc_enable_vd1(struct meson_drm *priv)static void meson_g12a_crtc_enable_vd1 (struct meson_drm *priv) { -writel_relaxed (((1 <<16 ) |/* post bld premult*/ - (1 <<8 ) |/* post src */ - (1 <<4 ) |/* pre bld premult*/ - (1 <<0 )), - priv->io_base +_REG (VD1_BLEND_SRC_CTRL )); +writel_relaxed (VD_BLEND_PREBLD_SRC_VD1 | +VD_BLEND_PREBLD_PREMULT_EN | +VD_BLEND_POSTBLD_SRC_VD1 | +VD_BLEND_POSTBLD_PREMULT_EN , + priv->io_base +_REG (VD1_BLEND_SRC_CTRL )); }void meson_crtc_irq (struct meson_drm *priv)
@@ -489,7 +489,12 @@ void meson_crtc_irq(struct meson_drm *priv)writel_relaxed (priv->viu.vd1_range_map_cr, priv->io_base + meson_crtc->viu_offset +_REG (VD1_IF0_RANGE_MAP_CR )); -writel_relaxed (0x78404 , +writel_relaxed (VPP_VSC_BANK_LENGTH (4 ) | +VPP_HSC_BANK_LENGTH (4 ) | +VPP_SC_VD_EN_ENABLE | +VPP_SC_TOP_EN_ENABLE | +VPP_SC_HSC_EN_ENABLE | +VPP_SC_VSC_EN_ENABLE , priv->io_base +_REG (VPP_SC_MISC ));writel_relaxed (priv->viu.vpp_pic_in_height, priv->io_base +_REG (VPP_PIC_IN_HEIGHT ));
drivers/gpu/drm/meson/meson_registers.h +16 -0
@@ -370,6 +370,12 @@#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17#define VPP_HSC_PHASE_CTRL 0x1d18#define VPP_SC_MISC 0x1d19 +#define VPP_SC_VD_EN_ENABLE BIT(15) +#define VPP_SC_TOP_EN_ENABLE BIT(16) +#define VPP_SC_HSC_EN_ENABLE BIT(17) +#define VPP_SC_VSC_EN_ENABLE BIT(18) +#define VPP_VSC_BANK_LENGTH (length) (length & 0x7) +#define VPP_HSC_BANK_LENGTH (length) ((length & 0x7) << 8)#define VPP_PREBLEND_VD1_H_START_END 0x1d1a#define VPP_PREBLEND_VD1_V_START_END 0x1d1b#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c
@@ -1638,6 +1644,16 @@#define VPP_SLEEP_CTRL 0x1dfa#define VD1_BLEND_SRC_CTRL 0x1dfb#define VD2_BLEND_SRC_CTRL 0x1dfc +#define VD_BLEND_PREBLD_SRC_VD1 (1 << 0) +#define VD_BLEND_PREBLD_SRC_VD2 (2 << 0) +#define VD_BLEND_PREBLD_SRC_OSD1 (3 << 0) +#define VD_BLEND_PREBLD_SRC_OSD2 (4 << 0) +#define VD_BLEND_PREBLD_PREMULT_EN BIT(4) +#define VD_BLEND_POSTBLD_SRC_VD1 (1 << 8) +#define VD_BLEND_POSTBLD_SRC_VD2 (2 << 8) +#define VD_BLEND_POSTBLD_SRC_OSD1 (3 << 8) +#define VD_BLEND_POSTBLD_SRC_OSD2 (4 << 8) +#define VD_BLEND_POSTBLD_PREMULT_EN BIT(16)#define OSD1_BLEND_SRC_CTRL 0x1dfd#define OSD2_BLEND_SRC_CTRL 0x1dfe
Signature · 1 line
2.17.1
PATCH 3/9 drm: meson: drv: use macro when initializing vpu
In reply to Julien MassonThis patch add new macro which is used to set WRARB/RDARB mode of the VPU.
--- drivers/gpu/drm/meson/meson_drv.c | 26 +++++++++++++++++++++---- drivers/gpu/drm/meson/meson_registers.h | 1 + 2 files changed, 23 insertions(+), 4 deletions(-)
drivers/gpu/drm/meson/meson_drv.c +22 -4
@@ -149,10 +149,28 @@ static struct regmap_config meson_regmap_config = {static void meson_vpu_init (struct meson_drm *priv) { -writel_relaxed (0x210000 , priv->io_base +_REG (VPU_RDARB_MODE_L1C1 )); -writel_relaxed (0x10000 , priv->io_base +_REG (VPU_RDARB_MODE_L1C2 )); -writel_relaxed (0x900000 , priv->io_base +_REG (VPU_RDARB_MODE_L2C1 )); -writel_relaxed (0x20000 , priv->io_base +_REG (VPU_WRARB_MODE_L2C1 )); +u32 value; + +/* +* Slave dc0 and dc5 connected to master port 1. +* By default other slaves are connected to master port 0. +*/ + value =VPU_RDARB_SLAVE_TO_MASTER_PORT (0 ,1 ) | +VPU_RDARB_SLAVE_TO_MASTER_PORT (5 ,1 ); +writel_relaxed (value, priv->io_base +_REG (VPU_RDARB_MODE_L1C1 )); + +/* Slave dc0 connected to master port 1 */ + value =VPU_RDARB_SLAVE_TO_MASTER_PORT (0 ,1 ); +writel_relaxed (value, priv->io_base +_REG (VPU_RDARB_MODE_L1C2 )); + +/* Slave dc4 and dc7 connected to master port 1 */ + value =VPU_RDARB_SLAVE_TO_MASTER_PORT (4 ,1 ) | +VPU_RDARB_SLAVE_TO_MASTER_PORT (7 ,1 ); +writel_relaxed (value, priv->io_base +_REG (VPU_RDARB_MODE_L2C1 )); + +/* Slave dc1 connected to master port 1 */ + value =VPU_RDARB_SLAVE_TO_MASTER_PORT (1 ,1 ); +writel_relaxed (value, priv->io_base +_REG (VPU_WRARB_MODE_L2C1 )); }static void meson_remove_framebuffers (void )
drivers/gpu/drm/meson/meson_registers.h +1 -0
@@ -1496,6 +1496,7 @@#define VPU_RDARB_MODE_L1C2 0x2799#define VPU_RDARB_MODE_L2C1 0x279d#define VPU_WRARB_MODE_L2C1 0x27a2 +#define VPU_RDARB_SLAVE_TO_MASTER_PORT (dc, port) (port << (16 + dc))/* osd super scale */ #define OSDSR_HV_SIZEIN 0x3130
Signature · 1 line
2.17.1
PATCH 4/9 drm: meson: vpp: use proper macros instead of magic constants
In reply to Julien MassonThis patch add new macros which are used to set the following registers:
- VPP_OSD_SCALE_COEF_IDX
- VPP_DOLBY_CTRL
- VPP_OFIFO_SIZE
- VPP_HOLD_LINES
- VPP_SC_MISC
- VPP_VADJ_CTRL
--- drivers/gpu/drm/meson/meson_registers.h | 8 ++++++++ drivers/gpu/drm/meson/meson_vpp.c | 27 ++++++++++++++++--------- 2 files changed, 25 insertions(+), 10 deletions(-)
drivers/gpu/drm/meson/meson_registers.h +8 -0
@@ -349,6 +349,7 @@#define VPP_LINE_IN_LENGTH 0x1d01#define VPP_PIC_IN_HEIGHT 0x1d02#define VPP_SCALE_COEF_IDX 0x1d03 +#define VPP_SCALE_HORIZONTAL_COEF BIT(8)#define VPP_SCALE_COEF 0x1d04#define VPP_VSC_REGION12_STARTP 0x1d05#define VPP_VSC_REGION34_STARTP 0x1d06
@@ -385,6 +386,8 @@#define VPP_PREBLEND_H_SIZE 0x1d20#define VPP_POSTBLEND_H_SIZE 0x1d21#define VPP_HOLD_LINES 0x1d22 +#define VPP_POSTBLEND_HOLD_LINES (lines) (lines & 0xf) +#define VPP_PREBLEND_HOLD_LINES (lines) ((lines & 0xf) << 8)#define VPP_BLEND_ONECOLOR_CTRL 0x1d23#define VPP_PREBLEND_CURRENT_XY 0x1d24#define VPP_POSTBLEND_CURRENT_XY 0x1d25
@@ -403,6 +406,8 @@#define VPP_OSD2_PREBLEND BIT(17)#define VPP_COLOR_MNG_ENABLE BIT(28)#define VPP_OFIFO_SIZE 0x1d27 +#define VPP_OFIFO_SIZE_MASK GENMASK(13, 0) +#define VPP_OFIFO_SIZE_DEFAULT (0xfff << 20 | 0x1000)#define VPP_FIFO_STATUS 0x1d28#define VPP_SMOKE_CTRL 0x1d29#define VPP_SMOKE1_VAL 0x1d2a
@@ -418,6 +423,8 @@#define VPP_HSC_PHASE_CTRL1 0x1d34#define VPP_HSC_INI_PAT_CTRL 0x1d35#define VPP_VADJ_CTRL 0x1d40 +#define VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1) +#define VPP_VADJ1_Y 0x1d41#define VPP_VADJ1_MA_MB 0x1d42#define VPP_VADJ1_MC_MD 0x1d43
@@ -477,6 +484,7 @@#define VPP_PEAKING_VGAIN 0x1d92#define VPP_PEAKING_NLP_1 0x1d93#define VPP_DOLBY_CTRL 0x1d93 +#define VPP_PPS_DUMMY_DATA_MODE (1 << 17)#define VPP_PEAKING_NLP_2 0x1d94#define VPP_PEAKING_NLP_3 0x1d95#define VPP_PEAKING_NLP_4 0x1d96
drivers/gpu/drm/meson/meson_vpp.c +17 -10
@@ -57,7 +57,7 @@ static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv, {int i; -writel_relaxed (is_horizontal ?BIT (8 ) :0 , +writel_relaxed (is_horizontal ?VPP_SCALE_HORIZONTAL_COEF :0 , priv->io_base +_REG (VPP_OSD_SCALE_COEF_IDX ));for (i =0 ; i <33 ; i++) writel_relaxed(coefs[i],
@@ -82,7 +82,7 @@ static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv, {int i; -writel_relaxed (is_horizontal ?BIT (8 ) :0 , +writel_relaxed (is_horizontal ?VPP_SCALE_HORIZONTAL_COEF :0 , priv->io_base +_REG (VPP_SCALE_COEF_IDX ));for (i =0 ; i <33 ; i++) writel_relaxed(coefs[i],
@@ -97,20 +97,22 @@ void meson_vpp_init(struct meson_drm *priv)else if (meson_vpu_is_compatible (priv,"amlogic,meson-gxm-vpu" )) {writel_bits_relaxed (0xff <<16 ,0xff <<16 , priv->io_base +_REG (VIU_MISC_CTRL1 )); -writel_relaxed (0x20000 , priv->io_base +_REG (VPP_DOLBY_CTRL )); -writel_relaxed (0x1020080 , +writel_relaxed (VPP_PPS_DUMMY_DATA_MODE , + priv->io_base +_REG (VPP_DOLBY_CTRL )); +writel_relaxed (0x108080 , priv->io_base +_REG (VPP_DUMMY_DATA1 )); }else if (meson_vpu_is_compatible (priv,"amlogic,meson-g12a-vpu" ))writel_relaxed (0xf , priv->io_base +_REG (DOLBY_PATH_CTRL ));/* Initialize vpu fifo control registers */ if (meson_vpu_is_compatible (priv,"amlogic,meson-g12a-vpu" )) -writel_relaxed (0xfff <<20 |0x1000 , +writel_relaxed (VPP_OFIFO_SIZE_DEFAULT , priv->io_base +_REG (VPP_OFIFO_SIZE ));else -writel_relaxed (readl_relaxed (priv->io_base +_REG (VPP_OFIFO_SIZE )) | -0x77f , priv->io_base +_REG (VPP_OFIFO_SIZE )); -writel_relaxed (0x08080808 , priv->io_base +_REG (VPP_HOLD_LINES )); +writel_bits_relaxed (VPP_OFIFO_SIZE_MASK ,0x77f , + priv->io_base +_REG (VPP_OFIFO_SIZE )); +writel_relaxed (VPP_POSTBLEND_HOLD_LINES (4 ) |VPP_PREBLEND_HOLD_LINES (4 ), + priv->io_base +_REG (VPP_HOLD_LINES ));if (!meson_vpu_is_compatible (priv,"amlogic,meson-g12a-vpu" )) {/* Turn off preblend */
@@ -138,10 +140,15 @@ void meson_vpp_init(struct meson_drm *priv)writel_relaxed (0 , priv->io_base +_REG (VPP_OSD_SC_CTRL0 ));writel_relaxed (0 , priv->io_base +_REG (VPP_OSD_VSC_CTRL0 ));writel_relaxed (0 , priv->io_base +_REG (VPP_OSD_HSC_CTRL0 )); -writel_relaxed (4 | (4 <<8 ) |BIT (15 ), + +/* Set horizontal/vertical bank length and enable video scale out */ +writel_relaxed (VPP_VSC_BANK_LENGTH (4 ) |VPP_HSC_BANK_LENGTH (4 ) | +VPP_SC_VD_EN_ENABLE , priv->io_base +_REG (VPP_SC_MISC )); -writel_relaxed (1 , priv->io_base +_REG (VPP_VADJ_CTRL )); +/* Enable minus black level for vadj1 */ +writel_relaxed (VPP_MINUS_BLACK_LVL_VADJ1_ENABLE , + priv->io_base +_REG (VPP_VADJ_CTRL ));/* Write in the proper filter coefficients. */ meson_vpp_write_scaling_filter_coefs(priv,
Signature · 1 line
2.17.1
PATCH 5/9 drm: meson: viu: use proper macros instead of magic constants
In reply to Julien MassonThis patch add new macros which are used to set the following registers:
- VIU_SW_RESET
- VIU_OSD1_CTRL_STAT
- VIU_OSD2_CTRL_STAT
- VIU_OSD1_FIFO_CTRL_STAT
- VIU_OSD2_FIFO_CTRL_STAT
- VIU_MISC_CTRL0
- VIU_OSD_BLEND_CTRL
- OSD1_BLEND_SRC_CTRL
- OSD2_BLEND_SRC_CTRL
- DOLBY_PATH_CTRL
--- drivers/gpu/drm/meson/meson_plane.c | 2 +- drivers/gpu/drm/meson/meson_registers.h | 27 ++++++++ drivers/gpu/drm/meson/meson_viu.c | 82 +++++++++++++------------ 3 files changed, 72 insertions(+), 39 deletions(-)
drivers/gpu/drm/meson/meson_plane.c +1 -1
@@ -318,7 +318,7 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,/* Disable OSD1 */ if (meson_vpu_is_compatible (priv,"amlogic,meson-g12a-vpu" )) -writel_bits_relaxed (3 <<8 ,0 , +writel_bits_relaxed (VIU_OSD1_POSTBLD_SRC_OSD1 ,0 , priv->io_base +_REG (OSD1_BLEND_SRC_CTRL ));else writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
drivers/gpu/drm/meson/meson_registers.h +27 -0
@@ -146,11 +146,19 @@#define VIU_ADDR_START 0x1a00#define VIU_ADDR_END 0x1aff#define VIU_SW_RESET 0x1a01 +#define VIU_SW_RESET_OSD1 BIT(0)#define VIU_MISC_CTRL0 0x1a06 +#define VIU_CTRL0_VD1_AFBC_MASK 0x170000#define VIU_MISC_CTRL1 0x1a07#define D2D3_INTF_LENGTH 0x1a08#define D2D3_INTF_CTRL0 0x1a09#define VIU_OSD1_CTRL_STAT 0x1a10 +#define VIU_OSD1_OSD_BLK_ENABLE BIT(0) +#define VIU_OSD1_POSTBLD_SRC_VD1 (1 << 8) +#define VIU_OSD1_POSTBLD_SRC_VD2 (2 << 8) +#define VIU_OSD1_POSTBLD_SRC_OSD1 (3 << 8) +#define VIU_OSD1_POSTBLD_SRC_OSD2 (4 << 8) +#define VIU_OSD1_OSD_ENABLE BIT(21)#define VIU_OSD1_CTRL_STAT2 0x1a2d#define VIU_OSD1_COLOR_ADDR 0x1a11#define VIU_OSD1_COLOR 0x1a12
@@ -240,6 +248,12 @@#define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f#define VIU_OSD3_DIMM_CTRL 0x3da0 +#define VIU_OSD_DDR_PRIORITY_URGENT BIT(0) +#define VIU_OSD_HOLD_FIFO_LINES (lines) ((lines & 0x1f) << 5) +#define VIU_OSD_FIFO_DEPTH_VAL (val) ((val & 0x7f) << 12) +#define VIU_OSD_WORDS_PER_BURST (words) (((words & 0x4) >> 1) << 22) +#define VIU_OSD_FIFO_LIMITS (size) ((size & 0xf) << 24) +#define VD1_IF0_GEN_REG 0x1a50#define VD1_IF0_CANVAS0 0x1a51#define VD1_IF0_CANVAS1 0x1a52
@@ -1620,10 +1634,18 @@#define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c#define DOLBY_PATH_CTRL 0x1a0c +#define DOLBY_BYPASS_EN (val) (val & 0xf)#define OSD_PATH_MISC_CTRL 0x1a0e#define MALI_AFBCD_TOP_CTRL 0x1a0f#define VIU_OSD_BLEND_CTRL 0x39b0 +#define VIU_OSD_BLEND_REORDER (dest, src) ((src) << (dest * 4)) +#define VIU_OSD_BLEND_DIN_EN (bits) ((bits & 0xf) << 20) +#define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24) +#define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25) +#define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26) +#define VIU_OSD_BLEND_BLEN2_PREMULT_EN (input) ((input & 0x3) << 27) +#define VIU_OSD_BLEND_HOLD_LINES (lines) ((lines & 0x7) << 29)#define VIU_OSD_BLEND_CTRL1 0x39c0#define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1#define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2
@@ -1665,6 +1687,11 @@#define VD_BLEND_POSTBLD_PREMULT_EN BIT(16)#define OSD1_BLEND_SRC_CTRL 0x1dfd#define OSD2_BLEND_SRC_CTRL 0x1dfe +#define OSD_BLEND_POSTBLD_SRC_VD1 (1 << 8) +#define OSD_BLEND_POSTBLD_SRC_VD2 (2 << 8) +#define OSD_BLEND_POSTBLD_SRC_OSD1 (3 << 8) +#define OSD_BLEND_POSTBLD_SRC_OSD2 (4 << 8) +#define OSD_BLEND_PATH_SEL_ENABLE BIT(20)#define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969
drivers/gpu/drm/meson/meson_viu.c +44 -38
126 lines not on this page · raw message
Signature · 1 line
2.17.1
PATCH 6/9 drm: meson: venc: use proper macros instead of magic constants
In reply to Julien MassonThis patch add new macros which are used to set the following registers:
- ENCI_CFILT_CTRL
- ENCI_CFILT_CTRL2
- ENCI_MACV_MAX_AMP
- ENCI_VIDEO_MODE_ADV
- ENCI_VFIFO2VD_CTL
- ENCI_VIDEO_EN
- ENCP_VIDEO_MODE
- VPU_HDMI_SETTING
- VENC_UPSAMPLE_CTRL0
- VENC_UPSAMPLE_CTRL1
- VENC_UPSAMPLE_CTRL2
- VENC_VDAC_FIFO_CTRL
- VENC_VDAC_DAC0_FILT_CTRL0
- VENC_INTCTRL
--- drivers/gpu/drm/meson/meson_registers.h | 51 ++++++++ drivers/gpu/drm/meson/meson_venc.c | 155 +++++++++++++++++++----- drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- 3 files changed, 177 insertions(+), 32 deletions(-)
drivers/gpu/drm/meson/meson_registers.h +51 -0
@@ -742,6 +742,25 @@#define VENC_UPSAMPLE_CTRL0 0x1b64#define VENC_UPSAMPLE_CTRL1 0x1b65#define VENC_UPSAMPLE_CTRL2 0x1b66 +#define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0) +#define VENC_UPSAMPLE_CTRL_F1_EN BIT(5) +#define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6) +#define VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA (0x0 << 12) +#define VENC_UPSAMPLE_CTRL_CVBS (0x1 << 12) +#define VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA (0x2 << 12) +#define VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA (0x3 << 12) +#define VENC_UPSAMPLE_CTRL_INTERLACE_PB (0x4 << 12) +#define VENC_UPSAMPLE_CTRL_INTERLACE_PR (0x5 << 12) +#define VENC_UPSAMPLE_CTRL_INTERLACE_R (0x6 << 12) +#define VENC_UPSAMPLE_CTRL_INTERLACE_G (0x7 << 12) +#define VENC_UPSAMPLE_CTRL_INTERLACE_B (0x8 << 12) +#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y (0x9 << 12) +#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB (0xa << 12) +#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR (0xb << 12) +#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_R (0xc << 12) +#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_G (0xd << 12) +#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_B (0xe << 12) +#define VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE (0xf << 12)#define TCON_INVERT_CTL 0x1b67#define VENC_VIDEO_PROG_MODE 0x1b68#define VENC_ENCI_LINE 0x1b69
@@ -750,6 +769,7 @@#define VENC_ENCP_PIXEL 0x1b6c#define VENC_STATA 0x1b6d#define VENC_INTCTRL 0x1b6e +#define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1)#define VENC_INTFLAG 0x1b6f#define VENC_VIDEO_TST_EN 0x1b70#define VENC_VIDEO_TST_MDSEL 0x1b71
@@ -760,6 +780,7 @@#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77#define VENC_VDAC_DACSEL0 0x1b78 +#define VENC_VDAC_SEL_ATV_DMD BIT(5)#define VENC_VDAC_DACSEL1 0x1b79#define VENC_VDAC_DACSEL2 0x1b7a#define VENC_VDAC_DACSEL3 0x1b7b
@@ -780,6 +801,7 @@#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa#define VENC_VDAC_DAC5_OFFSET 0x1bfb#define VENC_VDAC_FIFO_CTRL 0x1bfc +#define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13)#define ENCL_TCON_INVERT_CTL 0x1bfd#define ENCP_VIDEO_EN 0x1b80#define ENCP_VIDEO_SYNC_MODE 0x1b81
@@ -795,6 +817,7 @@#define ENCP_VIDEO_SYNC_OFFST 0x1b8b#define ENCP_VIDEO_MACV_OFFST 0x1b8c#define ENCP_VIDEO_MODE 0x1b8d +#define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14)#define ENCP_VIDEO_MODE_ADV 0x1b8e#define ENCP_DBG_PX_RST 0x1b90#define ENCP_DBG_LN_RST 0x1b91
@@ -873,6 +896,11 @@#define C656_FS_LNED 0x1be7#define ENCI_VIDEO_MODE 0x1b00#define ENCI_VIDEO_MODE_ADV 0x1b01 +#define ENCI_VIDEO_MODE_ADV_DMXMD (val) (val & 0x3) +#define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2) +#define ENCI_VIDEO_MODE_ADV_YBW_MEDIUM (0 << 4) +#define ENCI_VIDEO_MODE_ADV_YBW_LOW (0x1 << 4) +#define ENCI_VIDEO_MODE_ADV_YBW_HIGH (0x2 << 4)#define ENCI_VIDEO_FSC_ADJ 0x1b02#define ENCI_VIDEO_BRIGHT 0x1b03#define ENCI_VIDEO_CONT 0x1b04
@@ -943,13 +971,17 @@#define ENCI_DBG_MAXPX 0x1b4c#define ENCI_DBG_MAXLN 0x1b4d#define ENCI_MACV_MAX_AMP 0x1b50 +#define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15) +#define ENCI_MACV_MAX_AMP_VAL (val) (val & 0x83ff)#define ENCI_MACV_PULSE_LO 0x1b51#define ENCI_MACV_PULSE_HI 0x1b52#define ENCI_MACV_BKP_MAX 0x1b53#define ENCI_CFILT_CTRL 0x1b54 +#define ENCI_CFILT_CMPT_SEL_HIGH BIT(1)#define ENCI_CFILT7 0x1b55#define ENCI_YC_DELAY 0x1b56#define ENCI_VIDEO_EN 0x1b57 +#define ENCI_VIDEO_EN_ENABLE BIT(0)#define ENCI_DVI_HSO_BEGIN 0x1c00#define ENCI_DVI_HSO_END 0x1c01#define ENCI_DVI_VSO_BLINE_EVN 0x1c02
@@ -961,6 +993,10 @@#define ENCI_DVI_VSO_END_EVN 0x1c08#define ENCI_DVI_VSO_END_ODD 0x1c09#define ENCI_CFILT_CTRL2 0x1c0a +#define ENCI_CFILT_CMPT_CR_DLY (delay) (delay & 0xf) +#define ENCI_CFILT_CMPT_CB_DLY (delay) ((delay & 0xf) << 4) +#define ENCI_CFILT_CVBS_CR_DLY (delay) ((delay & 0xf) << 8) +#define ENCI_CFILT_CVBS_CB_DLY (delay) ((delay & 0xf) << 12)#define ENCI_DACSEL_0 0x1c0b#define ENCI_DACSEL_1 0x1c0c#define ENCP_DACSEL_0 0x1c0d
@@ -975,6 +1011,8 @@#define ENCI_TST_CLRBAR_WIDTH 0x1c16#define ENCI_TST_VDCNT_STSET 0x1c17#define ENCI_VFIFO2VD_CTL 0x1c18 +#define ENCI_VFIFO2VD_CTL_ENABLE BIT(0) +#define ENCI_VFIFO2VD_CTL_VD_SEL (val) ((val & 0xff) << 8)#define ENCI_VFIFO2VD_PIXEL_START 0x1c19#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b
@@ -1037,6 +1075,7 @@#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 +#define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0)#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b
@@ -1442,6 +1481,18 @@#define VIU2_SEL_VENC_ENCP (2 << 2)#define VIU2_SEL_VENC_ENCT (3 << 2)#define VPU_HDMI_SETTING 0x271b +#define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0) +#define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1) +#define VPU_HDMI_INV_HSYNC BIT(2) +#define VPU_HDMI_INV_VSYNC BIT(3) +#define VPU_HDMI_OUTPUT_CRYCB (0 << 5) +#define VPU_HDMI_OUTPUT_YCBCR (1 << 5) +#define VPU_HDMI_OUTPUT_YCRCB (2 << 5) +#define VPU_HDMI_OUTPUT_CBCRY (3 << 5) +#define VPU_HDMI_OUTPUT_CBYCR (4 << 5) +#define VPU_HDMI_OUTPUT_CRCBY (5 << 5) +#define VPU_HDMI_WR_RATE (rate) (((rate & 0x1f) - 1) << 8) +#define VPU_HDMI_RD_RATE (rate) (((rate & 0x1f) - 1) << 12)#define ENCI_INFO_READ 0x271c#define ENCP_INFO_READ 0x271d#define ENCT_INFO_READ 0x271e
drivers/gpu/drm/meson/meson_venc.c +124 -31
266 lines not on this page · raw message
drivers/gpu/drm/meson/meson_venc_cvbs.c +2 -1
@@ -172,7 +172,8 @@ static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)struct meson_drm *priv = meson_venc_cvbs->priv;/* VDAC0 source is not from ATV */ -writel_bits_relaxed (BIT (5 ),0 , priv->io_base +_REG (VENC_VDAC_DACSEL0 )); +writel_bits_relaxed (VENC_VDAC_SEL_ATV_DMD ,0 , + priv->io_base +_REG (VENC_VDAC_DACSEL0 ));if (meson_vpu_is_compatible (priv,"amlogic,meson-gxbb-vpu" )) {regmap_write (priv->hhi,HHI_VDAC_CNTL0 ,1 );
Signature · 1 line
2.17.1
PATCH 7/9 drm: meson: global clean-up
In reply to Julien MassonThis patch aims to:
- Add general and TODO comments
- Respect coding style for multi-line comments
- Align macro definitions
- Remove useless macro
--- drivers/gpu/drm/meson/meson_dw_hdmi.c | 2 ++ drivers/gpu/drm/meson/meson_dw_hdmi.h | 12 ++++++---- drivers/gpu/drm/meson/meson_registers.h | 31 +++++++++++-------------- drivers/gpu/drm/meson/meson_vclk.c | 4 +++- drivers/gpu/drm/meson/meson_venc.c | 10 ++++---- 5 files changed, 33 insertions(+), 26 deletions(-)
drivers/gpu/drm/meson/meson_dw_hdmi.c +2 -0
@@ -428,6 +428,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */ dw_hdmi_top_write_bits (dw_hdmi,HDMITX_TOP_CLK_CNTL ,0x3 ,0x3 ); + +/* Enable cec_clk and hdcp22_tmdsclk_en */ dw_hdmi_top_write_bits (dw_hdmi,HDMITX_TOP_CLK_CNTL ,0x3 <<4 ,0x3 <<4 );
drivers/gpu/drm/meson/meson_dw_hdmi.h +8 -4
@@ -100,7 +100,8 @@#define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6)#define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7) -/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; +/* +* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
@@ -135,7 +136,8 @@/* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ #define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B) -/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, +/* +* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, * used when TMDS CLK rate = TMDS character rate /4. Default 0. * Bit 0 R Reserved. Default 0. * [ 1] shift_tmds_clk_pttn
@@ -143,12 +145,14 @@*/ #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C) -/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM +/* +* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM * failure, write 1 to clear the failure flag. Default 0. */ #define HDMITX_TOP_REVOCMEM_STAT (0x00D) -/* Bit 1 R filtered RxSense status +/* +* Bit 1 R filtered RxSense status * Bit 0 R filtered HPD status. */ #define HDMITX_TOP_STAT0 (0x00E)
drivers/gpu/drm/meson/meson_registers.h +14 -17
@@ -406,19 +406,19 @@#define VPP_PREBLEND_CURRENT_XY 0x1d24#define VPP_POSTBLEND_CURRENT_XY 0x1d25#define VPP_MISC 0x1d26 -#define VPP_PREBLEND_ENABLE BIT(6) -#define VPP_POSTBLEND_ENABLE BIT(7) -#define VPP_OSD2_ALPHA_PREMULT BIT(8) -#define VPP_OSD1_ALPHA_PREMULT BIT(9) -#define VPP_VD1_POSTBLEND BIT(10) -#define VPP_VD2_POSTBLEND BIT(11) -#define VPP_OSD1_POSTBLEND BIT(12) -#define VPP_OSD2_POSTBLEND BIT(13) -#define VPP_VD1_PREBLEND BIT(14) -#define VPP_VD2_PREBLEND BIT(15) -#define VPP_OSD1_PREBLEND BIT(16) -#define VPP_OSD2_PREBLEND BIT(17) -#define VPP_COLOR_MNG_ENABLE BIT(28) +#define VPP_PREBLEND_ENABLE BIT(6) +#define VPP_POSTBLEND_ENABLE BIT(7) +#define VPP_OSD2_ALPHA_PREMULT BIT(8) +#define VPP_OSD1_ALPHA_PREMULT BIT(9) +#define VPP_VD1_POSTBLEND BIT(10) +#define VPP_VD2_POSTBLEND BIT(11) +#define VPP_OSD1_POSTBLEND BIT(12) +#define VPP_OSD2_POSTBLEND BIT(13) +#define VPP_VD1_PREBLEND BIT(14) +#define VPP_VD2_PREBLEND BIT(15) +#define VPP_OSD1_PREBLEND BIT(16) +#define VPP_OSD2_PREBLEND BIT(17) +#define VPP_COLOR_MNG_ENABLE BIT(28)#define VPP_OFIFO_SIZE 0x1d27#define VPP_OFIFO_SIZE_MASK GENMASK(13, 0)#define VPP_OFIFO_SIZE_DEFAULT (0xfff << 20 | 0x1000)
@@ -629,6 +629,7 @@#define OSD34_SCI_WH_M1 0x3d29#define OSD34_SCO_H_START_END 0x3d2a#define OSD34_SCO_V_START_END 0x3d2b +/* viu2 */ #define VIU2_ADDR_START 0x1e00#define VIU2_ADDR_END 0x1eff
@@ -1611,7 +1612,6 @@#define OSD1_AFBCD_STATUS 0x31a8#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa -#define VIU_MISC_CTRL1 0x1a07/* add for gxm and 962e dv core2 */ #define DOLBY_CORE2A_SWAP_CTRL1 0x3434
@@ -1626,8 +1626,6 @@#define VPU_MAFBC_COMMAND 0x3a05#define VPU_MAFBC_STATUS 0x3a06#define VPU_MAFBC_SURFACE_CFG 0x3a07 - -/* osd afbc on g12a */ #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12
@@ -1748,6 +1746,5 @@#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969#define VPP_RDARB_MODE 0x3978#define VPP_RDARB_REQEN_SLV 0x3979 -#define VPU_RDARB_MODE_L2C1 0x279d#endif /* __MESON_REGISTERS_H */
drivers/gpu/drm/meson/meson_vclk.c +3 -1
@@ -495,6 +495,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,regmap_write (priv->hhi,HHI_HDMI_PLL_CNTL ,0x0b3a0400 | m);/* Enable and reset */ +/* TODO: add specific macro for g12a here */ regmap_update_bits (priv->hhi,HHI_HDMI_PLL_CNTL ,0x3 <<28 ,0x3 <<28 );
@@ -969,7 +970,8 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,meson_venci_cvbs_clock_config (priv);return ; }else if (target ==MESON_VCLK_TARGET_DMT ) { -/* The DMT clock path is fixed after the PLL: +/* +* The DMT clock path is fixed after the PLL: * - automatic PLL freq + OD management * - vid_pll_div = VID_PLL_DIV_5 * - vclk_div = 2
drivers/gpu/drm/meson/meson_venc.c +6 -4
@@ -61,9 +61,9 @@/* HHI Registers */ #define HHI_GCLK_MPEG2 0x148/* 0x52 offset in data sheet */ #define HHI_VDAC_CNTL0 0x2F4/* 0xbd offset in data sheet */ -#define HHI_VDAC_CNTL0_G12A 0x2EC/* 0xbd offset in data sheet */ +#define HHI_VDAC_CNTL0_G12A 0x2EC/* 0xbb offset in data sheet */ #define HHI_VDAC_CNTL1 0x2F8/* 0xbe offset in data sheet */ -#define HHI_VDAC_CNTL1_G12A 0x2F0/* 0xbe offset in data sheet */ +#define HHI_VDAC_CNTL1_G12A 0x2F0/* 0xbc offset in data sheet */ #define HHI_HDMI_PHY_CNTL0 0x3a0/* 0xe8 offset in data sheet */ struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
@@ -1085,7 +1085,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,writel_relaxed (vmode->enci.video_mode, priv->io_base +_REG (ENCI_VIDEO_MODE )); -/* Advanced Video Mode : +/* +* Advanced Video Mode : * Demux shifting 0x2 * Blank line end at line17/22 * High bandwidth Luma Filter
@@ -1599,7 +1600,8 @@ void meson_venci_cvbs_mode_set(struct meson_drm *priv,writel_relaxed (mode->video_mode, priv->io_base +_REG (ENCI_VIDEO_MODE )); -/* Advanced Video Mode : +/* +* Advanced Video Mode : * Demux shifting 0x2 * Blank line end at line17/22 * High bandwidth Luma Filter
Signature · 1 line
2.17.1
PATCH 8/9 drm: meson: add macro used to enable HDMI PLL
In reply to Julien MassonThis patch add new macro HHI_HDMI_PLL_CNTL_EN which is used to enable HDMI PLL.
--- drivers/gpu/drm/meson/meson_vclk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/gpu/drm/meson/meson_vclk.c +2 -1
@@ -96,6 +96,7 @@#define HHI_VDAC_CNTL1 0x2F8/* 0xbe offset in data sheet */ #define HHI_HDMI_PLL_CNTL 0x320/* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_EN BIT(30)#define HHI_HDMI_PLL_CNTL2 0x324/* 0xc9 offset in data sheet */ #define HHI_HDMI_PLL_CNTL3 0x328/* 0xca offset in data sheet */ #define HHI_HDMI_PLL_CNTL4 0x32C/* 0xcb offset in data sheet */
@@ -468,7 +469,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,/* Enable and unreset */ regmap_update_bits (priv->hhi,HHI_HDMI_PLL_CNTL , -0x7 <<28 ,0x4 <<28 ); +0x7 <<28 ,HHI_HDMI_PLL_CNTL_EN );/* Poll for lock bit */ regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
Signature · 1 line
2.17.1
PATCH 9/9 drm: meson: venc: set the correct macrovision max amplitude value
In reply to Julien MassonAccording to the register description of ENCI_MACV_MAX_AMP, the macrovision max amplitude value should be:
- hdmi 480i => 0xb
- hdmi 576i => 0x7
The max value is 0x7ff (10 bits).
--- drivers/gpu/drm/meson/meson_venc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/gpu/drm/meson/meson_venc.c +2 -2
@@ -192,7 +192,7 @@ union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = { .hso_end = 129, .vso_even = 3, .vso_odd = 260, - .macv_max_amp = 0x810b, + .macv_max_amp = 0xb, .video_prog_mode = 0xf0, .video_mode = 0x8, .sch_adjust = 0x20,
@@ -212,7 +212,7 @@ union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = { .hso_end = 129, .vso_even = 3, .vso_odd = 260, - .macv_max_amp = 8107, + .macv_max_amp = 0x7, .video_prog_mode = 0xff, .video_mode = 0x13, .sch_adjust = 0x28,
Signature · 1 line
2.17.1
Kevin Hilman
maintainerRe: [PATCH 4/9] drm: meson: vpp: use proper macros instead of magic constants
In reply to Julien MassonQuoted 10 lines · Julien Masson
This patch add new macros which are used to set the following registers:
-VPP_OSD_SCALE_COEF_IDX
-VPP_DOLBY_CTRL
-VPP_OFIFO_SIZE
-VPP_HOLD_LINES
-VPP_SC_MISC
-VPP_VADJ_CTRLSigned-off-by Julien Masson <[email protected]>
[...]
drivers/gpu/drm/meson/meson_vpp.c void meson_vpp_init(struct meson_drm *priv) · line 102
Quoted 9 lines
drivers/gpu/drm/meson/meson_vpp.c +3
-2@@ -97,20 +97,22 @@ void meson_vpp_init(struct meson_drm *priv)else if (meson_vpu_is_compatible (priv,"amlogic,meson-gxm-vpu" )) {writel_bits_relaxed (0xff <<16 ,0xff <<16 , priv->io_base +_REG (VIU_MISC_CTRL1 )); -writel_relaxed (0x20000 , priv->io_base +_REG (VPP_DOLBY_CTRL )); - writel_relaxed(0x1020080, +writel_relaxed (VPP_PPS_DUMMY_DATA_MODE , + priv->io_base +_REG (VPP_DOLBY_CTRL )); + writel_relaxed(0x108080,
nit: still a magic constant here, and it's not obvious why it's different from the current one.
Kevin
Kevin Hilman
maintainerRe: [PATCH 8/9] drm: meson: add macro used to enable HDMI PLL
In reply to Julien MassonQuoted 21 lines · Julien Masson
This patch add new macro
HHI_HDMI_PLL_CNTL_ENwhich is used to enable HDMI PLL.Signed-off-by Julien Masson <[email protected]>--- drivers/gpu/drm/meson/meson_vclk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/gpu/drm/meson/meson_vclk.c +1
-0@@ -96,6 +96,7 @@#define HHI_VDAC_CNTL1 0x2F8/* 0xbe offset in data sheet */ #define HHI_HDMI_PLL_CNTL 0x320/* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_EN BIT(30)#define HHI_HDMI_PLL_CNTL2 0x324/* 0xc9 offset in data sheet */ #define HHI_HDMI_PLL_CNTL3 0x328/* 0xca offset in data sheet */ #define HHI_HDMI_PLL_CNTL4 0x32C/* 0xcb offset in data sheet */
drivers/gpu/drm/meson/meson_vclk.c void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, · line 472
Quoted 5 lines
drivers/gpu/drm/meson/meson_vclk.c +1
-1@@ -468,7 +469,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,/* Enable and unreset */ regmap_update_bits (priv->hhi,HHI_HDMI_PLL_CNTL , -0x7 <<28 ,0x4 <<28 ); +0x7 <<28 ,HHI_HDMI_PLL_CNTL_EN );
still using a magic const for the mask. Can use GENMASK() for this?
Kevin
Kevin Hilman
maintainerQuoted 10 lines · Julien Masson
This patch series aims to clean-up differents parts of the drm meson code source.
Couple macros have been defined and used to set several registers instead of using magic constants.
I also took the opportunity to:
- add/remove/update comments
- remove useless code
- minor fix/improvment
Nice set of cleanups, thanks! I especially like the extra in-code comments.
Could you also add to the cover-letter how this was tested, and on what platforms so we know it's not going to introduce any regressions.
Thanks,
Kevin
Re: [PATCH 4/9] drm: meson: vpp: use proper macros instead of magic constants
In reply to Kevin HilmanQuoted 15 lines · Kevin Hilman
Quoted 10 lines · Julien Masson
This patch add new macros which are used to set the following registers:
-VPP_OSD_SCALE_COEF_IDX
-VPP_DOLBY_CTRL
-VPP_OFIFO_SIZE
-VPP_HOLD_LINES
-VPP_SC_MISC
-VPP_VADJ_CTRLSigned-off-by Julien Masson <[email protected]>[...]
Quoted 12 lines
drivers/gpu/drm/meson/meson_vpp.c void meson_vpp_init(struct meson_drm *priv) · line 102
Quoted 9 lines
drivers/gpu/drm/meson/meson_vpp.c +3
-2@@ -97,20 +97,22 @@ void meson_vpp_init(struct meson_drm *priv)else if (meson_vpu_is_compatible (priv,"amlogic,meson-gxm-vpu" )) {writel_bits_relaxed (0xff <<16 ,0xff <<16 , priv->io_base +_REG (VIU_MISC_CTRL1 )); -writel_relaxed (0x20000 , priv->io_base +_REG (VPP_DOLBY_CTRL )); - writel_relaxed(0x1020080, +writel_relaxed (VPP_PPS_DUMMY_DATA_MODE , + priv->io_base +_REG (VPP_DOLBY_CTRL )); + writel_relaxed(0x108080,nit: still a magic constant here, and it's not obvious why it's different from the current one.
This is a magic constant, it's a color, but indeed it should not change.
0x1020080 is the 10bit variant of 0x108080, on purpose.
Neil
Quoted 3 lines
Kevin
_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 8/9] drm: meson: add macro used to enable HDMI PLL
In reply to Kevin HilmanQuoted 24 lines · Kevin Hilman
Quoted 22 lines · Julien Masson
This patch add new macro
HHI_HDMI_PLL_CNTL_ENwhich is used to enable HDMI PLL.Signed-off-by Julien Masson <[email protected]>--- drivers/gpu/drm/meson/meson_vclk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/gpu/drm/meson/meson_vclk.c +1
-0@@ -96,6 +96,7 @@#define HHI_VDAC_CNTL1 0x2F8/* 0xbe offset in data sheet */ #define HHI_HDMI_PLL_CNTL 0x320/* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_EN BIT(30)#define HHI_HDMI_PLL_CNTL2 0x324/* 0xc9 offset in data sheet */ #define HHI_HDMI_PLL_CNTL3 0x328/* 0xca offset in data sheet */ #define HHI_HDMI_PLL_CNTL4 0x32C/* 0xcb offset in data sheet */ @@ -468,7 +469,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
Quoted 4 lines
drivers/gpu/drm/meson/meson_vclk.c void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, · line 472
Quoted 4 lines
drivers/gpu/drm/meson/meson_vclk.c +1
-1/* Enable and unreset */ regmap_update_bits (priv->hhi,HHI_HDMI_PLL_CNTL , -0x7 <<28 ,0x4 <<28 ); +0x7 <<28 ,HHI_HDMI_PLL_CNTL_EN );
I'll do a pass on the PLL part since it needs much more work than a cleanup, it's ok for me.
Neil
Quoted 5 lines
still using a magic const for the mask. Can use
GENMASK()for this?Kevin
Neil Armstrong
Reviewed-byQuoted 16 lines · Kevin Hilman
Quoted 10 lines · Julien Masson
This patch series aims to clean-up differents parts of the drm meson code source.
Couple macros have been defined and used to set several registers instead of using magic constants.
I also took the opportunity to:
- add/remove/update comments
- remove useless code
- minor fix/improvmentNice set of cleanups, thanks! I especially like the extra in-code comments.
Quoted 7 lines
Could you also add to the cover-letter how this was tested, and on what platforms so we know it's not going to introduce any regressions.
Thanks,
Kevin
Apart the wrong magic value in patch 4 that I'll fix while applying,
I'll run a few tests on all the supported SoC versions:
- GXBB
- GXL
- GXM
- G12A/G12B
and push to drm-misc-next.
Neil
Hi Julien,
Quoted 25 lines · Neil Armstrong
Quoted 16 lines · Kevin Hilman
Quoted 10 lines · Julien Masson
This patch series aims to clean-up differents parts of the drm meson code source.
Couple macros have been defined and used to set several registers instead of using magic constants.
I also took the opportunity to:
- add/remove/update comments
- remove useless code
- minor fix/improvmentNice set of cleanups, thanks! I especially like the extra in-code comments.
Quoted 7 lines
Could you also add to the cover-letter how this was tested, and on what platforms so we know it's not going to introduce any regressions.
Thanks,
Kevin
Quoted 8 lines
Apart the wrong magic value in patch 4 that I'll fix while applying,
Reviewed-by Neil Armstrong <[email protected]>I'll run a few tests on all the supported SoC versions:
- GXBB
- GXL
- GXM
- G12A/G12B
Tested on :
- 1024x768x60 DVI Dell monitor
- 3840x2160x60 HDMI2.0 Samsung TV
Tested :
- Simple DMT mode
- Advanced HDMI2.0 4k60 mode with SCDC negotiation and scrambling
- OSD layer and scaling
- Video layer and scaling
SoCs:
- GXBB: meson-gxbb-odroidc2
modetest -M meson -s 32:1024x768-60 -P 33@37:1024x768@AR24 -P 35@37:1024x768@NV12 modetest -M meson -s 32:1024x768-60 -P 33@37:1024x768@AR24 -P 35@37:1024x768*2@NV12 modetest -M meson -s 32:1024x768-60 -P 33@37:512x384*2@AR24 -P 35@37:2048x1536*0.5@NV12
modetest -M meson -s 32:3840x2160-60 -P 33@37:3840x2160@AR24 -P 35@37:3840x2160@NV12 modetest -M meson -s 32:3840x2160-60 -P 33@37:1920x1080*2@AR24 -P 35@37:3840x2160*0.8@NV12
No visual issues
- GXL: meson-gxl-s905x-libretech-cc
modetest -M meson -s 34:1024x768-60 -P 35@39:1024x768@AR24 -P 37@39:1024x768@NV12 modetest -M meson -s 34:1024x768-60 -P 35@39:1024x768@AR24 -P 37@39:1024x768*2@NV12 modetest -M meson -s 34:1024x768-60 -P 35@39:512x384*2@AR24 -P 37@39:2048x1536*0.5@NV12 modetest -M meson -s 34:3840x2160-60 -P 35@39:3840x2160@AR24 -P 37@39:3840x2160@NV12 modetest -M meson -s 34:3840x2160-60 -P 35@39:1920x1080*2@AR24 -P 37@39:3840x2160*0.8@NV12
No visual issues
- GXM: meson-gxm-khadas-vim2
modetest -M meson -s 32:1024x768-60 -P 33@37:1024x768@AR24 -P 35@37:1024x768@NV12 modetest -M meson -s 32:1024x768-60 -P 33@37:1024x768@AR24 -P 35@37:1024x768*2@NV12 modetest -M meson -s 32:1024x768-60 -P 33@37:512x384*2@AR24 -P 35@37:2048x1536*0.5@NV12
modetest -M meson -s 32:3840x2160-60 -P 33@37:3840x2160@AR24 -P 35@37:3840x2160@NV12 modetest -M meson -s 32:3840x2160-60 -P 33@37:1920x1080*2@AR24 -P 35@37:3840x2160*0.8@NV12
With the following fix on patch 4:
========><====================================
drivers/gpu/drm/meson/meson_vpp.c +1 -1
@@ -98,7 +98,7 @@ void meson_vpp_init(struct meson_drm *priv) priv->io_base + _REG(VIU_MISC_CTRL1));writel_relaxed (VPP_PPS_DUMMY_DATA_MODE , priv->io_base +_REG (VPP_DOLBY_CTRL )); -writel_relaxed (0x108080 , +writel_relaxed (0x1020080 , priv->io_base +_REG (VPP_DUMMY_DATA1 )); }else if (meson_vpu_is_compatible (priv,"amlogic,meson-g12a-vpu" ))writel_relaxed (0xf , priv->io_base +_REG (DOLBY_PATH_CTRL ));
========><====================================
No visual issues
- G12A/G12B: meson-g12a-sei510
Issue found in patch 5, the following fix will be applied while applying onto drm-misc-next :
========><====================================
drivers/gpu/drm/meson/meson_viu.c +1 -1
@@ -407,7 +407,7 @@ void meson_viu_init(struct meson_drm *priv)VIU_OSD_BLEND_HOLD_LINES (4 ), priv->io_base + _REG(VIU_OSD_BLEND_CTRL)); -writel_relaxed (VIU_OSD1_POSTBLD_SRC_OSD1 , +writel_relaxed (OSD_BLEND_PATH_SEL_ENABLE , priv->io_base +_REG (OSD1_BLEND_SRC_CTRL ));writel_relaxed (OSD_BLEND_PATH_SEL_ENABLE , priv->io_base +_REG (OSD2_BLEND_SRC_CTRL ));
========><====================================
modetest -M meson -s 34:800x600 -P 35@39:800x600@AR24 -P 37@39:800x600@NV12 modetest -M meson -s 34:800x600 -P 35@39:800x600@AR24 -P 37@39:800x600*2@NV12 modetest -M meson -s 34:800x600 -P 35@39:400x300*2@AR24 -P 37@39:1600x600*0.5@NV12 modetest -M meson -s 34:3840x2160-60 -P 35@39:3840x2160@AR24 -P 37@39:3840x2160@NV12 modetest -M meson -s 34:3840x2160-60 -P 35@39:1920x1080*2@AR24 -P 37@39:3840x2160*0.8@NV12
No visual issues
Quoted 5 lines
and push to drm-misc-next.
Neil
Applying to drm-misc-next with the fixes
Neil