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x86: tsc: Add missing Cherrytrail frequency to the table

PATCH In review Compostella, Jeremy 2 participants 3 messages May 11, 2016 – May 12, 2016 x86

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Compostella, Jeremy

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#0 lore raw

PATCH 1/1 x86: tsc: Add missing Cherrytrail frequency to the table

Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4 means that the CPU reference clock runs at 80MHz. Add this missing frequency to the table.

Signed-off-by Jeremy Compostella <[email protected]>
---
 arch/x86/kernel/tsc_msr.c | 3 +++
 1 file changed, 3 insertions(+)
arch/x86/kernel/tsc_msr.c +3 -0
index 6aa0f4d..89694a7 100644
@@ -23,6 +23,7 @@
 #include <asm/param.h>
 
 /* CPU reference clock frequency: in KHz */
+#define FREQ_80		80000
 #define FREQ_83		83200
 #define FREQ_100	99840
 #define FREQ_133	133200

@@ -56,6 +57,8 @@ static struct freq_desc freq_desc_tables[] = {
 	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
 	/* ANN */
 	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+	/* AIRMONT */
+	{ 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80, 0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)
Signature · 1 line
1.9.1
author
#1 lore raw

Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4 means that the CPU reference clock runs at 80MHz. Add this missing frequency to the table.

Signed-off-by Jeremy Compostella <[email protected]>
---
 arch/x86/kernel/tsc_msr.c | 4 ++++
 1 file changed, 4 insertions(+)
arch/x86/kernel/tsc_msr.c +4 -0
index 6aa0f4d..ab271a7 100644
@@ -23,6 +23,7 @@
 #include <asm/param.h>
 
 /* CPU reference clock frequency: in KHz */
+#define FREQ_80		80000
 #define FREQ_83		83200
 #define FREQ_100	99840
 #define FREQ_133	133200

@@ -56,6 +57,9 @@ static struct freq_desc freq_desc_tables[] = {
 	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
 	/* ANN */
 	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+	/* AIRMONT */
+	{ 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80,
+			0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)
Signature · 1 line
1.9.1
merge bot
#2 lore raw

[tip:x86/urgent] x86/tsc: Add missing Cherrytrail frequency to the table

x86/tsc: Add missing Cherrytrail frequency to the table
Commit-ID:  e2724e9d969294879936daf7833d4adda26c8efc
Gitweb:     http://git.kernel.org/tip/e2724e9d969294879936daf7833d4adda26c8efc
Author:     Jeremy Compostella <[email protected]>
AuthorDate: Wed, 11 May 2016 17:23:34 +0200
Committer:  Thomas Gleixner <[email protected]>
CommitDate: Thu, 12 May 2016 14:27:14 +0200

x86/tsc: Add missing Cherrytrail frequency to the table

Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4 means that the CPU reference clock runs at 80MHz. Add this missing frequency to the table.

Signed-off-by Jeremy Compostella <[email protected]>
Link http://lkml.kernel.org/r/[email protected] open here
Signed-off-by Thomas Gleixner <[email protected]>
---
 arch/x86/kernel/tsc_msr.c | 3 +++
 1 file changed, 3 insertions(+)
arch/x86/kernel/tsc_msr.c +3 -0
index 6aa0f4d..9911a06 100644
@@ -23,6 +23,7 @@
 #include <asm/param.h>
 
 /* CPU reference clock frequency: in KHz */
+#define FREQ_80		80000
 #define FREQ_83		83200
 #define FREQ_100	99840
 #define FREQ_133	133200

@@ -56,6 +57,8 @@ static struct freq_desc freq_desc_tables[] = {
 	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
 	/* ANN */
 	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+	/* AIRMONT */
+	{ 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80,	0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)