PM: proposed branch for PM collaboration

index e0d1b1f..a272720 100644
@@ -82,6 +82,8 @@ static void per_gpio_clk_disable(void)
 		clk_disable(gpio_fcks[i-1]);
 }
 
+static struct kobject *suspend_dir_kobj;
+
 /* XXX This is for gpio fclk hack. Will be removed as gpio driver
  * handles fcks correctly */
 static void gpio_fclk_mask(u32 *fclk)

@@ -306,6 +308,7 @@ int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 {
 	u32 cur_state;
 	int ret = 0;
+	int sleep_switch = 0;
 
 	if (pwrdm == NULL || IS_ERR(pwrdm))
 		return -EINVAL;

@@ -315,6 +318,16 @@ int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 	if (cur_state == state)
 		return ret;
 
+	/* Check if we need to wake-up the pwrdm for state switch */
+	/* MPU, core and per are never in sleep states when we are here*/
+	if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
+		if ((cm_read_mod_reg(pwrdm->prcm_offs, 0x48) & 0x3) == 0x3) {
+			sleep_switch = 1;
+			cm_rmw_mod_reg_bits(0x3, 0x2, pwrdm->prcm_offs, 0x48);
+			pwrdm_wait_transition(pwrdm);
+		}
+	}
+
 	pwrdm_for_each_clkdm(pwrdm, _clkdm_deny_idle);
 
 	ret = pwrdm_set_next_pwrst(pwrdm, state);

@@ -326,6 +339,12 @@ int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 
 	pwrdm_for_each_clkdm(pwrdm, _clkdm_allow_idle);
 
+	if (sleep_switch) {
+		cm_rmw_mod_reg_bits(0x3, 0x3, pwrdm->prcm_offs, 0x48);
+		pwrdm_wait_transition(pwrdm);
+		pm_dbg_pwrdm_state_switch(pwrdm);
+	}
+
 err:
 	return ret;
 }

@@ -380,7 +399,6 @@ static int omap3_pm_suspend(void)
 restore:
 	/* Restore next_pwrsts */
 	list_for_each_entry(pwrst, &pwrst_list, node) {
-		set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 		if (state != pwrst->next_state) {
 			printk(KERN_INFO "Powerdomain (%s) didn't enter "

@@ -388,6 +406,7 @@ restore:
 			       pwrst->pwrdm->name, pwrst->next_state);
 			ret = -1;
 		}
+		set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 	}
 	if (ret)
 		printk(KERN_ERR "Could not enter target state in pm_suspend\n");

@@ -584,9 +603,67 @@ static void __init prcm_setup_regs(void)
 			OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
 }
 
+static struct power_state *get_pwrst_node(const char *name)
+{
+	struct powerdomain *pwrdm;
+	struct power_state *pwrst_tmp;
+	struct power_state *pwrst = NULL;
+
+	pwrdm = pwrdm_lookup(name);
+
+	if (pwrdm == NULL) {
+		printk(KERN_ERR "pwrdm not found %s\n", name);
+		return NULL;
+	}
+
+	list_for_each_entry(pwrst_tmp, &pwrst_list, node)
+		if (pwrst_tmp->pwrdm == pwrdm)
+			pwrst = pwrst_tmp;
+
+	if (pwrst == NULL)
+		printk(KERN_ERR "pwrdm not in suspend list %s\n", name);
+
+	return pwrst;
+}
+
+static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *attr,
+			 char *buf)
+{
+	struct power_state *pwrst;
+
+	pwrst = get_pwrst_node(attr->attr.name);
+
+	if (pwrst == NULL)
+		return -EINVAL;
+
+	return sprintf(buf, "%hu\n", pwrst->next_state);
+}
+
+static ssize_t state_store(struct kobject *kobj, struct kobj_attribute *attr,
+			  const char *buf, size_t n)
+{
+	struct power_state *pwrst;
+	unsigned short value;
+
+	if (sscanf(buf, "%hu", &value) != 1 || value > PWRDM_POWER_ON) {
+		printk(KERN_ERR "state_store: Invalid value\n");
+		return -EINVAL;
+	}
+
+	pwrst = get_pwrst_node(attr->attr.name);
+
+	if (pwrst == NULL)
+		return -EINVAL;
+
+	pwrst->next_state = value;
+
+	return n;
+}
+
 static int __init pwrdms_setup(struct powerdomain *pwrdm)
 {
 	struct power_state *pwrst;
+	struct kobj_attribute *attr;
 
 	if (!pwrdm->pwrsts)
 		return 0;

@@ -601,6 +678,18 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
 	if (pwrdm_has_hdwr_sar(pwrdm))
 		pwrdm_enable_hdwr_sar(pwrdm);
 
+	attr = kmalloc(sizeof(struct kobj_attribute), GFP_KERNEL);
+	if (!attr)
+		return -ENOMEM;
+
+	attr->attr.name = pwrdm->name;
+	attr->attr.mode = 0644;
+	attr->show = state_show;
+	attr->store = state_store;
+
+	if (sysfs_create_file(suspend_dir_kobj, &(attr->attr)))
+		return -ENOMEM;
+
 	return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 }
 

@@ -625,6 +714,12 @@ int __init omap3_pm_init(void)
 		goto err1;
 	}
 
+	suspend_dir_kobj = kobject_create_and_add("suspend_config", power_kobj);
+	if (!suspend_dir_kobj) {
+		ret = -ENOMEM;
+		goto err2;
+	}
+
 	ret = pwrdm_for_each(pwrdms_setup);
 	if (ret) {
 		printk(KERN_ERR "Failed to setup powerdomains\n");

index 88c8ef4..a5fc5b0 100644
@@ -39,6 +39,7 @@
 #include "cm.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
+#include "pm.h"
 
 #define MAX_CLOCK_ENABLE_WAIT		100000
 

@@ -1025,5 +1026,6 @@ void omap2_clk_disable_unused(struct clk *clk)
 
 	printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
 	_omap2_clk_disable(clk);
+	pm_dbg_clk_state_switch(clk);
 }
 #endif

index fa62f14..9670ed1 100644
@@ -36,6 +36,8 @@
 #include <mach/powerdomain.h>
 #include <mach/clockdomain.h>
 
+#include "pm.h"
+
 /* clkdm_list contains all registered struct clockdomains */
 static LIST_HEAD(clkdm_list);
 

@@ -567,6 +569,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
 	else
 		omap2_clkdm_wakeup(clkdm);
 
+	pm_dbg_clkdm_state_switch(clkdm);
+
 	return 0;
 }
 

@@ -618,6 +622,29 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 	else
 		omap2_clkdm_sleep(clkdm);
 
+	pm_dbg_clkdm_state_switch(clkdm);
+
+	return 0;
+}
+
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+int clkdm_dbg_show_counters(struct seq_file *s, void *unused)
+{
+	struct clockdomain *clkdm;
+
+	list_for_each_entry(clkdm, &clkdm_list, node) {
+		if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
+			strcmp(clkdm->name, "wkup_clkdm") == 0)
+			continue;
+		seq_printf(s, "%s->%s (%d)", clkdm->name,
+			   clkdm->pwrdm.ptr->name,
+			   atomic_read(&clkdm->usecount));
+		seq_printf(s, "\n");
+	}
+
 	return 0;
 }
 
+#endif

416 lines not on this page · raw message

index b8aae08..c063565 100644
@@ -28,6 +28,8 @@
 #include <asm/mach/time.h>
 #include <asm/atomic.h>
 
+#include <mach/powerdomain.h>
+
 #include <mach/pm.h>
 #include "pm.h"
 

index 60a386d..19da5c7 100644
@@ -28,7 +28,36 @@ extern void omap2_allow_sleep(void);
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
 extern int omap2_pm_debug;
 #else
-#define omap2_pm_dump(mode, resume, us)		do {} while (0);
-#define omap2_pm_debug				0
+#define omap2_pm_dump(mode, resume, us) do {} while (0);
+#define omap2_pm_debug 0
+#endif
+
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+struct seq_file;
+struct clk;
+struct clockdomain;
+struct powerdomain;
+extern int pm_dbg_pwrdm_state_switch(struct powerdomain *pwrdm);
+extern int pm_dbg_clkdm_state_switch(struct clockdomain *clkdm);
+extern int pm_dbg_clk_state_switch(struct clk *clk);
+extern int pm_dbg_pre_suspend(void);
+extern int pm_dbg_post_suspend(void);
+extern int pm_dbg_regset_save(int reg_set);
+extern int pm_dbg_regset_init(int reg_set);
+extern int pwrdm_dbg_show_counters(struct seq_file *s, void *unused);
+extern int pwrdm_dbg_show_timers(struct seq_file *s, void *unused);
+extern int clkdm_dbg_show_counters(struct seq_file *s, void *unused);
+extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
+#else
+#define pm_dbg_pwrdm_state_switch(domain) do; while (0)
+#define pm_dbg_clkdm_state_switch(domain) do; while (0)
+#define pm_dbg_clk_state_switch(domain) do; while (0)
+#define pm_dbg_pre_suspend() do; while (0)
+#define pm_dbg_post_suspend() do; while (0)
+#define pm_dbg_regset_save(reg_set) do; while (0)
+#define pm_dbg_regset_init(reg_set) do; while (0)
+#define pwrdm_dbg_show_counters(s,unused) do; while (0)
+#define pwrdm_dbg_show_timers(s,unused) do; while (0)
+#define clkdm_dbg_show_counters(s,unused) do; while (0)
 #endif /* CONFIG_PM_DEBUG */
 #endif

index 32922ae..e0d1b1f 100644
@@ -208,6 +208,8 @@ static void omap_sram_idle(void)
 		return;
 	}
 
+	pm_dbg_pre_suspend();
+
 	omap2_gpio_prepare_for_retention();
 
 	/* Disable GPIO clocks if allowed */

@@ -225,6 +227,8 @@ static void omap_sram_idle(void)
 	per_gpio_clk_enable();
 
 	omap2_gpio_resume_after_retention();
+
+	pm_dbg_post_suspend();
 }
 
 /*

@@ -298,7 +302,7 @@ static int _clkdm_allow_idle(struct powerdomain *pwrdm,
 /* This sets pwrdm state (other than mpu & core. Currently only ON &
  * RET are supported. Function is assuming that clkdm doesn't have
  * hw_sup mode enabled. */
-static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 {
 	u32 cur_state;
 	int ret = 0;

73 lines not on this page · raw message

index 4948cb7..8785cb7 100644
@@ -116,7 +116,12 @@ struct powerdomain {
 	struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
 
 	struct list_head node;
-
+#ifdef CONFIG_PM_DEBUG
+	int state;
+	int state_counter[4];
+	s64 timer;
+	s64 state_timer[4];
+#endif
 };
 
 

index 1b14bcf..b00f5f4 100644
@@ -37,138 +37,6 @@
 #ifdef CONFIG_PM_DEBUG
 int omap2_pm_debug = 0;
 
-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
-	serial_console_next_disable = omap2_read_32k_sync_counter();
-	/* Keep the clocks on for 4 secs */
-	serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
-	static const unsigned long uart_bases[3] = {
-		0x4806a000, 0x4806c000, 0x4806e000
-	};
-	unsigned long lsr_reg;
-	int looped = 0;
-
-	/* Wait for TX FIFO and THR to get empty */
-	lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
-	while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
-		looped = 1;
-	if (looped)
-		serial_console_kick();
-}
-
-u32 omap2_read_32k_sync_counter(void)
-{
-        return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
-	switch (serial_console_uart)  {
-	case 1:
-		*f1 &= ~(1 << 21);
-		break;
-	case 2:
-		*f1 &= ~(1 << 22);
-		break;
-	case 3:
-		*f2 &= ~(1 << 2);
-		break;
-	}
-}
-
-void serial_console_sleep(int enable)
-{
-	if (console_iclk == NULL || console_fclk == NULL)
-		return;
-
-	if (enable) {
-		BUG_ON(serial_console_clock_disabled);
-		if (clk_get_usecount(console_fclk) == 0)
-			return;
-		if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
-			return;
-		serial_wait_tx();
-		clk_disable(console_iclk);
-		clk_disable(console_fclk);
-		serial_console_clock_disabled = 1;
-	} else {
-		int serial_wakeup = 0;
-		u32 l;
-
-		switch (serial_console_uart)  {
-		case 1:
-			l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
-			if (l & OMAP24XX_ST_UART1)
-				serial_wakeup = 1;
-			break;
-		case 2:
-			l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
-			if (l & OMAP24XX_ST_UART2)
-				serial_wakeup = 1;
-			break;
-		case 3:
-			l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
-			if (l & OMAP24XX_ST_UART3)
-				serial_wakeup = 1;
-			break;
-		}
-		if (serial_wakeup)
-			serial_console_kick();
-		if (!serial_console_clock_disabled)
-			return;
-		clk_enable(console_iclk);
-		clk_enable(console_fclk);
-		serial_console_clock_disabled = 0;
-	}
-}
-
-void pm_init_serial_console(void)
-{
-	const struct omap_serial_console_config *conf;
-	char name[16];
-
-	conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
-			       struct omap_serial_console_config);
-	if (conf == NULL)
-		return;
-	if (conf->console_uart > 3 || conf->console_uart < 1)
-		return;
-	serial_console_uart = conf->console_uart;
-	sprintf(name, "uart%d_fck", conf->console_uart);
-	console_fclk = clk_get(NULL, name);
-	if (IS_ERR(console_fclk))
-		console_fclk = NULL;
-	name[6] = 'i';
-	console_iclk = clk_get(NULL, name);
-	if (IS_ERR(console_fclk))
-		console_iclk = NULL;
-	if (console_fclk == NULL || console_iclk == NULL) {
-		serial_console_uart = 0;
-		return;
-	}
-	switch (serial_console_uart) {
-	case 1:
-		prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1);
-		break;
-	case 2:
-		prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1);
-		break;
-	case 3:
-		prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD, OMAP24XX_PM_WKEN2);
-		break;
-	}
-}
-
 #define DUMP_PRM_MOD_REG(mod, reg)    \
 	regs[reg_count].name = #mod "." #reg; \
 	regs[reg_count++].val = prm_read_mod_reg(mod, reg)

index 1de5f14..b8aae08 100644
@@ -33,6 +33,7 @@
 
 unsigned short enable_dyn_sleep;
 unsigned short gpio_clocks_off_while_idle;
+unsigned short uart_clocks_off_while_idle;
 atomic_t sleep_block = ATOMIC_INIT(0);
 
 static ssize_t idle_show(struct kobject *, struct kobj_attribute *, char *);

@@ -45,6 +46,9 @@ static struct kobj_attribute sleep_while_idle_attr =
 static struct kobj_attribute gpio_clocks_off_while_idle_attr =
 	__ATTR(gpio_clocks_off_while_idle, 0644, idle_show, idle_store);
 
+static struct kobj_attribute uart_clocks_off_while_idle_attr =
+	__ATTR(uart_clocks_off_while_idle, 0644, idle_show, idle_store);
+
 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
 			 char *buf)
 {

@@ -52,6 +56,8 @@ static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
 		return sprintf(buf, "%hu\n", enable_dyn_sleep);
 	else if (attr == &gpio_clocks_off_while_idle_attr)
 		return sprintf(buf, "%hu\n", gpio_clocks_off_while_idle);
+	else if (attr == &uart_clocks_off_while_idle_attr)
+		return sprintf(buf, "%hu\n", uart_clocks_off_while_idle);
 	else
 		return -EINVAL;
 }

@@ -71,6 +77,8 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 		enable_dyn_sleep = value;
 	else if (attr == &gpio_clocks_off_while_idle_attr)
 		gpio_clocks_off_while_idle = value;
+	else if (attr == &uart_clocks_off_while_idle_attr)
+		uart_clocks_off_while_idle = value;
 	else
 		return -EINVAL;
 

@@ -111,6 +119,13 @@ static int __init omap_pm_init(void)
 		return error;
 	}
 	error = sysfs_create_file(power_kobj,
+				  &uart_clocks_off_while_idle_attr.attr);
+	if (error) {
+		printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
+		return error;
+	}
+
+	error = sysfs_create_file(power_kobj,
 				  &gpio_clocks_off_while_idle_attr.attr);
 	if (error)
 		printk(KERN_ERR "sysfs_create_file failed: %d\n", error);

index d446ea4..60a386d 100644
@@ -18,25 +18,17 @@ extern int omap3_pm_init(void);
 
 extern unsigned short enable_dyn_sleep;
 extern unsigned short gpio_clocks_off_while_idle;
+extern unsigned short uart_clocks_off_while_idle;
 extern atomic_t sleep_block;
 
 extern void omap2_block_sleep(void);
 extern void omap2_allow_sleep(void);
 
-
 #ifdef CONFIG_PM_DEBUG
-extern u32 omap2_read_32k_sync_counter(void);
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
-extern void serial_console_fclk_mask(u32 *f1, u32 *f2);
-extern void pm_init_serial_console(void);
-extern void serial_console_sleep(int enable);
 extern int omap2_pm_debug;
 #else
-#define omap2_read_32k_sync_counter()		0
-#define serial_console_sleep(enable)		do {} while (0);
-#define pm_init_serial_console()		do {} while (0);
 #define omap2_pm_dump(mode, resume, us)		do {} while (0);
-#define serial_console_fclk_mask(f1, f2)		do {} while (0);
 #define omap2_pm_debug				0
 #endif /* CONFIG_PM_DEBUG */
 #endif

121 lines not on this page · raw message

index 0baf359..32922ae 100644
@@ -29,6 +29,7 @@
 #include <mach/pm.h>
 #include <mach/clockdomain.h>
 #include <mach/powerdomain.h>
+#include <mach/common.h>
 
 #include "cm.h"
 #include "cm-regbits-34xx.h"

@@ -96,6 +97,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 	u32 wkst, irqstatus_mpu;
 	u32 fclk, iclk;
 
+	/* Check if we woke up to serial console activity */
+	omap_serial_check_wakeup();
+
 	/* WKUP */
 	wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
 	if (wkst) {

@@ -209,8 +213,14 @@ static void omap_sram_idle(void)
 	/* Disable GPIO clocks if allowed */
 	per_gpio_clk_disable();
 
+	/* Disable UART clocks if allowed */
+	omap_serial_enable_clocks(0);
+
 	_omap_sram_idle(NULL, save_state);
 
+	/* Enable UART clocks if allowed */
+	omap_serial_enable_clocks(1);
+
 	/* Enable GPIO clocks if allowed */
 	per_gpio_clk_enable();
 

@@ -248,6 +258,7 @@ static int omap3_fclks_active(void)
 				  CM_FCLKEN);
 
 	gpio_fclk_mask(&fck_per);
+	omap_serial_fclk_mask(&fck_core1, &fck_per);
 
 	if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 	    fck_cam | fck_per | fck_usbhost)

@@ -263,6 +274,8 @@ static int omap3_can_sleep(void)
 		return 0;
 	if (atomic_read(&sleep_block) > 0)
 		return 0;
+	if (!omap_serial_can_sleep())
+		return 0;
 	return 1;
 }
 

226 lines not on this page · raw message

index 5f46249..003c08e 100644
@@ -35,6 +35,9 @@ extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 extern void omap_serial_init(void);
 extern void omap_serial_enable_clocks(int enable);
+extern int omap_serial_can_sleep(void);
+extern void omap_serial_fclk_mask(u32 *f1, u32 *f2);
+void omap_serial_check_wakeup(void);
 #ifdef CONFIG_I2C_OMAP
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
 				 struct i2c_board_info const *info,

index 19da5c7..7776cdb 100644
@@ -24,6 +24,13 @@ extern atomic_t sleep_block;
 extern void omap2_block_sleep(void);
 extern void omap2_allow_sleep(void);
 
+#define SCRATCHPAD_ROM  		0x48002860
+#define SCRATCHPAD      		0x48002910
+#define SCRATHPAD_ROM_OFFSET    	0x19C
+#define TABLE_ADDRESS_OFFSET    	0x31
+#define TABLE_VALUE_OFFSET      	0x30
+#define CONTROL_REG_VALUE_OFFSET	0x32
+
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
 extern int omap2_pm_debug;

218 lines not on this page · raw message

index e4cf1c5..fd08490 100644
@@ -153,6 +153,11 @@ extern void omap1510_idle_loop_suspend(void);
 extern void omap1610_idle_loop_suspend(void);
 extern void omap24xx_idle_loop_suspend(void);
 
+extern void save_scratchpad_contents(void);
+extern void clear_scratchpad_contents(void);
+extern u32 *get_restore_pointer(void);
+extern void vfp_enable(void);
+
 extern unsigned int omap730_cpu_suspend_sz;
 extern unsigned int omap1510_cpu_suspend_sz;
 extern unsigned int omap1610_cpu_suspend_sz;

index 281c1c7..879d7c1 100644
@@ -83,6 +83,16 @@ static const u32 omap34xx_uart_padconf[OMAP_MAX_NR_PORTS] = {
 	CONTROL_PADCONF_UART3_RX
 };
 
+struct omap_uart_regs {
+	u16 dll;
+	u16 dlh;
+	u16 ier;
+	u16 sysc;
+	u16 scr;
+	u16 wer;
+};
+static struct omap_uart_regs uart_ctx[OMAP_MAX_NR_PORTS];
+
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
 		.membase	= IO_ADDRESS(OMAP_UART1_BASE),

@@ -314,6 +324,58 @@ static ssize_t awake_store(struct kobject *kobj, struct kobj_attribute *attr,
 	return n;
 }
 
+void omap_save_uart_ctx(int unum)
+{
+	u16 lcr = 0;
+
+	struct plat_serial8250_port *p = serial_platform_data + unum;
+
+	if (uart_ick[unum] == NULL)
+		return;
+
+	lcr = serial_read_reg(p, UART_LCR);
+	serial_write_reg(p, UART_LCR, 0xBF);
+	uart_ctx[unum].dll = serial_read_reg(p, UART_DLL);
+	uart_ctx[unum].dlh = serial_read_reg(p, UART_DLM);
+	serial_write_reg(p, UART_LCR, lcr);
+	uart_ctx[unum].ier = serial_read_reg(p, UART_IER);
+	uart_ctx[unum].sysc = serial_read_reg(p, UART_OMAP_SYSC);
+	uart_ctx[unum].scr = serial_read_reg(p, UART_OMAP_SCR);
+	uart_ctx[unum].wer = serial_read_reg(p, UART_OMAP_WER);
+}
+EXPORT_SYMBOL(omap_save_uart_ctx);
+
+void omap_restore_uart_ctx(int unum)
+{
+	u16 efr = 0;
+
+	struct plat_serial8250_port *p = serial_platform_data + unum;
+
+	if (uart_ick[unum] == NULL)
+		return;
+
+	serial_write_reg(p, UART_OMAP_MDR1, 0x7);
+	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+	efr = serial_read_reg(p, UART_EFR);
+	serial_write_reg(p, UART_EFR, UART_EFR_ECB);
+	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
+	serial_write_reg(p, UART_IER, 0x0);
+	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+	serial_write_reg(p, UART_DLL, uart_ctx[unum].dll);
+	serial_write_reg(p, UART_DLM, uart_ctx[unum].dlh);
+	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
+	serial_write_reg(p, UART_IER, uart_ctx[unum].ier);
+	serial_write_reg(p, UART_FCR, 0xA1);
+	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+	serial_write_reg(p, UART_EFR, efr);
+	serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
+	serial_write_reg(p, UART_OMAP_SCR, uart_ctx[unum].scr);
+	serial_write_reg(p, UART_OMAP_WER, uart_ctx[unum].wer);
+	serial_write_reg(p, UART_OMAP_SYSC, uart_ctx[unum].sysc);
+	serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
+}
+EXPORT_SYMBOL(omap_restore_uart_ctx);
+
 static struct platform_device serial_device = {
 	.name			= "serial8250",
 	.id			= PLAT8250_DEV_PLATFORM,

index 96c0d93..76ffd3c 100644
@@ -323,6 +323,7 @@
 #define UART_OMAP_MVER		0x14	/* Module version register */
 #define UART_OMAP_SYSC		0x15	/* System configuration register */
 #define UART_OMAP_SYSS		0x16	/* System status register */
+#define UART_OMAP_WER           0x17    /* Wake-up enable register */
 
 #endif /* _LINUX_SERIAL_REG_H */
 

index f3e0271..32f36fa 100644
@@ -54,6 +54,21 @@
 #define GPMC_CHUNK_SHIFT	24		/* 16 MB */
 #define GPMC_SECTION_SHIFT	28		/* 128 MB */
 
+/*
+ * Structure to save/restore gpmc context
+ * to support core off
+ */
+static struct gpmc_context {
+	u32 sysconfig;
+	u32 irqenable;
+	u32 timeout_ctrl;
+	u32 config;
+	u32 prefetch_config1;
+	u32 prefetch_config2;
+	u32 prefetch_control;
+	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
+} gpmc_ctx;
+
 static struct resource	gpmc_mem_root;
 static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);

@@ -451,3 +466,68 @@ void __init gpmc_init(void)
 
 	gpmc_mem_init();
 }
+
+void omap_save_gpmc_ctx()
+{
+	int i;
+	gpmc_ctx.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
+	gpmc_ctx.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
+	gpmc_ctx.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
+	gpmc_ctx.config = gpmc_read_reg(GPMC_CONFIG);
+	gpmc_ctx.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+	gpmc_ctx.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
+	gpmc_ctx.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
+	for (i = 0; i < GPMC_CS_NUM; i++) {
+		gpmc_ctx.cs_context[i].is_valid =
+				(gpmc_cs_read_reg(i, GPMC_CS_CONFIG7))
+								& (1 << 6);
+		if (gpmc_ctx.cs_context[i].is_valid) {
+			gpmc_ctx.cs_context[i].gpmc_config1 =
+				gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
+			gpmc_ctx.cs_context[i].gpmc_config2 =
+				gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
+			gpmc_ctx.cs_context[i].gpmc_config3 =
+				gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
+			gpmc_ctx.cs_context[i].gpmc_config4 =
+				gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
+			gpmc_ctx.cs_context[i].gpmc_config5 =
+				gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
+			gpmc_ctx.cs_context[i].gpmc_config6 =
+				gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
+			gpmc_ctx.cs_context[i].gpmc_config7 =
+				gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
+		}
+	}
+}
+
+void omap_restore_gpmc_ctx()
+{
+	int i;
+	gpmc_write_reg(GPMC_SYSCONFIG, gpmc_ctx.sysconfig);
+	gpmc_write_reg(GPMC_IRQENABLE, gpmc_ctx.irqenable);
+	gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_ctx.timeout_ctrl);
+	gpmc_write_reg(GPMC_CONFIG, gpmc_ctx.config);
+	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_ctx.prefetch_config1);
+	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_ctx.prefetch_config2);
+	gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_ctx.prefetch_control);
+	for (i = 0; i < GPMC_CS_NUM; i++) {
+		if (gpmc_ctx.cs_context[i].is_valid) {
+			gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
+					gpmc_ctx.cs_context[i].gpmc_config1);
+			gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
+					gpmc_ctx.cs_context[i].gpmc_config2);
+			gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
+					gpmc_ctx.cs_context[i].gpmc_config3);
+			gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
+					gpmc_ctx.cs_context[i].gpmc_config4);
+			gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
+					gpmc_ctx.cs_context[i].gpmc_config5);
+			gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
+					gpmc_ctx.cs_context[i].gpmc_config6);
+			gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
+					gpmc_ctx.cs_context[i].gpmc_config7);
+		}
+	}
+}
+
+

index 921b165..133991c 100644
@@ -90,6 +90,18 @@ struct gpmc_timings {
 	u16 wr_data_mux_bus;	/* WRDATAONADMUXBUS */
 };
 
+/* Structure to save gpmc cs context */
+struct gpmc_cs_config {
+	u32 gpmc_config1;
+	u32 gpmc_config2;
+	u32 gpmc_config3;
+	u32 gpmc_config4;
+	u32 gpmc_config5;
+	u32 gpmc_config6;
+	u32 gpmc_config7;
+	int is_valid;
+};
+
 extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
 extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);

@@ -103,6 +115,8 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
 extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
+extern void omap_save_gpmc_ctx(void);
+extern void omap_restore_gpmc_ctx(void);
 extern void __init gpmc_init(void);
 
 #endif

index 0f7cbe8..a661ed3 100644
@@ -503,6 +503,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 	omap_i2c_unidle(dev);
 
+	omap_i2c_init(dev);
+
 	if ((r = omap_i2c_wait_for_bb(dev)) < 0)
 		goto out;
 

index d696dde..d6acf6c 100644
@@ -815,12 +815,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
 	if (!pwrst)
 		return -ENOMEM;
 	pwrst->pwrdm = pwrdm;
-	if (!strcmp(pwrst->pwrdm->name, "core_pwrdm") ||
-			!strcmp(pwrst->pwrdm->name, "mpu_pwrdm") ||
-			!strcmp(pwrst->pwrdm->name, "mpu_pwrdm"))
-		pwrst->next_state = PWRDM_POWER_ON;
-	else
-		pwrst->next_state = PWRDM_POWER_OFF;
+	pwrst->next_state = PWRDM_POWER_RET;
 	list_add(&pwrst->node, &pwrst_list);
 
 	if (pwrdm_has_hdwr_sar(pwrdm))

@@ -838,7 +833,15 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
 	if (sysfs_create_file(suspend_dir_kobj, &(attr->attr)))
 		return -ENOMEM;
 
-	return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+#ifdef CONFIG_CPU_IDLE
+	/* Let cpuidle do selection here */
+	if (!strcmp(pwrst->pwrdm->name, "core_pwrdm") ||
+	    !strcmp(pwrst->pwrdm->name, "mpu_pwrdm") ||
+	    !strcmp(pwrst->pwrdm->name, "neon_pwrdm"))
+		return set_pwrdm_state(pwrst->pwrdm, PWRDM_POWER_ON);
+	else
+#endif
+		return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 }
 
 void omap_push_sram_idle()

index 4652136..1de5f14 100644
@@ -32,7 +32,7 @@
 #include "pm.h"
 
 unsigned short enable_dyn_sleep;
-unsigned short clocks_off_while_idle;
+unsigned short gpio_clocks_off_while_idle;
 atomic_t sleep_block = ATOMIC_INIT(0);
 
 static ssize_t idle_show(struct kobject *, struct kobj_attribute *, char *);

@@ -42,16 +42,16 @@ static ssize_t idle_store(struct kobject *k, struct kobj_attribute *,
 static struct kobj_attribute sleep_while_idle_attr =
 	__ATTR(sleep_while_idle, 0644, idle_show, idle_store);
 
-static struct kobj_attribute clocks_off_while_idle_attr =
-	__ATTR(clocks_off_while_idle, 0644, idle_show, idle_store);
+static struct kobj_attribute gpio_clocks_off_while_idle_attr =
+	__ATTR(gpio_clocks_off_while_idle, 0644, idle_show, idle_store);
 
 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
 			 char *buf)
 {
 	if (attr == &sleep_while_idle_attr)
 		return sprintf(buf, "%hu\n", enable_dyn_sleep);
-	else if (attr == &clocks_off_while_idle_attr)
-		return sprintf(buf, "%hu\n", clocks_off_while_idle);
+	else if (attr == &gpio_clocks_off_while_idle_attr)
+		return sprintf(buf, "%hu\n", gpio_clocks_off_while_idle);
 	else
 		return -EINVAL;
 }

@@ -69,8 +69,8 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 
 	if (attr == &sleep_while_idle_attr)
 		enable_dyn_sleep = value;
-	else if (attr == &clocks_off_while_idle_attr)
-		clocks_off_while_idle = value;
+	else if (attr == &gpio_clocks_off_while_idle_attr)
+		gpio_clocks_off_while_idle = value;
 	else
 		return -EINVAL;
 

@@ -106,10 +106,12 @@ static int __init omap_pm_init(void)
 	/* disabled till drivers are fixed */
 	enable_dyn_sleep = 0;
 	error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
-	if (error)
+	if (error) {
 		printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
+		return error;
+	}
 	error = sysfs_create_file(power_kobj,
-				  &clocks_off_while_idle_attr.attr);
+				  &gpio_clocks_off_while_idle_attr.attr);
 	if (error)
 		printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 

index 68c9278..d446ea4 100644
@@ -17,7 +17,7 @@ extern int omap2_pm_init(void);
 extern int omap3_pm_init(void);
 
 extern unsigned short enable_dyn_sleep;
-extern unsigned short clocks_off_while_idle;
+extern unsigned short gpio_clocks_off_while_idle;
 extern atomic_t sleep_block;
 
 extern void omap2_block_sleep(void);

88 lines not on this page · raw message

245 lines not on this page · raw message

56 lines not on this page · raw message

index a272720..8feab92 100644
@@ -185,7 +185,7 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static void omap_sram_idle(void)
+void omap_sram_idle(void)
 {
 	/* Variable to tell what needs to be saved and restored
 	 * in omap_sram_idle*/

@@ -200,6 +200,7 @@ static void omap_sram_idle(void)
 
 	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 	switch (mpu_next_state) {
+	case PWRDM_POWER_ON:
 	case PWRDM_POWER_RET:
 		/* No need to save context */
 		save_state = 0;

@@ -737,7 +738,9 @@ int __init omap3_pm_init(void)
 
 	suspend_set_ops(&omap_pm_ops);
 
+#ifndef CONFIG_CPU_IDLE
 	pm_idle = omap3_pm_idle;
+#endif
 
 	/* XXX This is for gpio fclk hack. Will be removed as gpio driver
 	 * handles fcks correctly */

index 42fa546..73f32a0 100644
@@ -60,7 +60,7 @@ u32 restore_pointer_address;
 
 static LIST_HEAD(pwrst_list);
 
-static void (*_omap_sram_idle)(u32 *addr, int save_state);
+void (*_omap_sram_idle)(u32 *addr, int save_state);
 
 static void (*saved_idle)(void);
 

index 73f32a0..ae324b4 100644
@@ -479,21 +479,7 @@ static void omap3_pm_idle(void)
 	if (!omap_serial_can_sleep())
 		goto out;
 
-	omap2_gpio_prepare_for_retention();
-
-	omap_serial_enable_clocks(0, 0);
-	omap_serial_enable_clocks(0, 1);
-	omap_serial_enable_clocks(0, 2);
-	per_gpio_clk_disable();
-
 	omap_sram_idle();
-
-	omap_serial_enable_clocks(1, 0);
-	omap_serial_enable_clocks(1, 1);
-	omap_serial_enable_clocks(1, 2);
-	per_gpio_clk_enable();
-
-	omap2_gpio_resume_after_retention();
 out:
 	local_fiq_enable();
 	local_irq_enable();

index 99ecd75..ee58873 100644
@@ -82,8 +82,12 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 
 	/* Program MPU to target state */
 	if (cx->mpu_state < PWRDM_POWER_ON) {
-		if (neon_pwrst == PWRDM_POWER_ON)
-			pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+		if (neon_pwrst == PWRDM_POWER_ON) {
+			if (cx->mpu_state == PWRDM_POWER_RET)
+				pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+			else if (cx->mpu_state == PWRDM_POWER_OFF)
+				pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
+		}
 		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
 	}
 

@@ -97,9 +101,13 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 		pwrdm_set_next_pwrst(core_pd, cx->core_state);
 	}
 
+	*(scratchpad_restore_addr) = restore_pointer_address;
+
 	/* Execute ARM wfi */
 	omap_sram_idle();
 
+	*(scratchpad_restore_addr) = 0x0;
+
 	/* Program MPU/NEON to ON */
 	if (cx->mpu_state < PWRDM_POWER_ON) {
 		if (neon_pwrst == PWRDM_POWER_ON)

@@ -207,7 +215,7 @@ void omap_init_power_states(void)
 						CPUIDLE_FLAG_BALANCED;
 
 	/* C3 . MPU OFF + Core active */
-	omap3_power_states[3].valid = 0;
+	omap3_power_states[3].valid = 1;
 	omap3_power_states[3].type = OMAP3_STATE_C3;
 	omap3_power_states[3].sleep_latency = 1500;
 	omap3_power_states[3].wakeup_latency = 1800;

@@ -229,7 +237,7 @@ void omap_init_power_states(void)
 			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
 
 	/* C5 . MPU OFF + Core CSWR */
-	omap3_power_states[5].valid = 0;
+	omap3_power_states[5].valid = 1;
 	omap3_power_states[5].type = OMAP3_STATE_C5;
 	omap3_power_states[5].sleep_latency = 3000;
 	omap3_power_states[5].wakeup_latency = 8500;

@@ -266,6 +274,9 @@ int omap3_idle_init(void)
 	struct cpuidle_state *state;
 	struct cpuidle_device *dev;
 
+	clear_scratchpad_contents();
+	save_scratchpad_contents();
+
 	omap_init_power_states();
 	cpuidle_register_driver(&omap3_idle_driver);
 

index 46ed51e..f2ebe68 100644
@@ -40,6 +40,11 @@ extern void per_gpio_clk_enable(void);
 extern void per_gpio_clk_disable(void);
 extern void omap_serial_enable_clocks(int enable);
 extern int omap3_can_sleep();
+extern void clear_scratchpad_contents(void);
+extern void save_scratchpad_contents(void);
+extern u32 *scratchpad_restore_addr;
+extern u32 restore_pointer_address;
+
 struct omap3_processor_cx {
 	u8 valid;
 	u8 type;

index ac55616..401120f 100644
@@ -101,6 +101,7 @@
 #define OMAP24XX_GPIO_IRQSTATUS2	0x0028
 #define OMAP24XX_GPIO_IRQENABLE2	0x002c
 #define OMAP24XX_GPIO_IRQENABLE1	0x001c
+#define OMAP24XX_GPIO_WAKE_EN		0x0020
 #define OMAP24XX_GPIO_CTRL		0x0030
 #define OMAP24XX_GPIO_OE		0x0034
 #define OMAP24XX_GPIO_DATAIN		0x0038

@@ -217,6 +218,22 @@ static struct gpio_bank gpio_bank_34xx[6] = {
 	{ OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
 };
 
+struct gpio_restore_regs {
+	u32 gpio_sysconfig;
+	u32 gpio_irqenable1;
+	u32 gpio_irqenable2;
+	u32 gpio_wake_en;
+	u32 gpio_ctrl;
+	u32 gpio_oe;
+	u32 gpio_leveldetect0;
+	u32 gpio_leveldetect1;
+	u32 gpio_risingdetect;
+	u32 gpio_fallingdetect;
+	u32 gpio_dataout;
+	u32 gpio_setwkuena;
+	u32 gpio_setdataout;
+};
+static struct gpio_restore_regs gpio_restore_banks[6];
 #endif
 
 static struct gpio_bank *gpio_bank;

@@ -1707,6 +1724,81 @@ void omap2_gpio_resume_after_retention(void)
 
 #endif
 
+#ifdef CONFIG_ARCH_OMAP34XX
+/* save the registers of bank 2-6 */
+void omap_gpio_save(void)
+{
+	int i;
+	/* saving banks from 2-6 only */
+	for (i = 1; i < gpio_bank_count; i++) {
+		struct gpio_bank *bank = &gpio_bank[i];
+		gpio_restore_banks[i].gpio_sysconfig =
+			__raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
+		gpio_restore_banks[i].gpio_irqenable1 =
+			__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+		gpio_restore_banks[i].gpio_irqenable2 =
+			__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+		gpio_restore_banks[i].gpio_wake_en =
+			__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
+		gpio_restore_banks[i].gpio_ctrl =
+			__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+		gpio_restore_banks[i].gpio_oe =
+			__raw_readl(bank->base + OMAP24XX_GPIO_OE);
+		gpio_restore_banks[i].gpio_leveldetect0 =
+			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+		gpio_restore_banks[i].gpio_leveldetect1 =
+			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+		gpio_restore_banks[i].gpio_risingdetect =
+			__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+		gpio_restore_banks[i].gpio_fallingdetect =
+			__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+		gpio_restore_banks[i].gpio_dataout =
+			__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
+		gpio_restore_banks[i].gpio_setwkuena =
+			__raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
+		gpio_restore_banks[i].gpio_setdataout =
+			__raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
+	}
+}
+EXPORT_SYMBOL(omap_gpio_save);
+
+/* restore the required registers of bank 2-6 */
+void omap_gpio_restore(void)
+{
+	int i;
+	for (i = 1; i < gpio_bank_count; i++) {
+		struct gpio_bank *bank = &gpio_bank[i];
+		__raw_writel(gpio_restore_banks[i].gpio_sysconfig,
+				bank->base + OMAP24XX_GPIO_SYSCONFIG);
+		__raw_writel(gpio_restore_banks[i].gpio_irqenable1,
+				bank->base + OMAP24XX_GPIO_IRQENABLE1);
+		__raw_writel(gpio_restore_banks[i].gpio_irqenable2,
+				bank->base + OMAP24XX_GPIO_IRQENABLE2);
+		__raw_writel(gpio_restore_banks[i].gpio_wake_en,
+				bank->base + OMAP24XX_GPIO_WAKE_EN);
+		__raw_writel(gpio_restore_banks[i].gpio_ctrl,
+				bank->base + OMAP24XX_GPIO_CTRL);
+		__raw_writel(gpio_restore_banks[i].gpio_oe,
+				bank->base + OMAP24XX_GPIO_OE);
+		__raw_writel(gpio_restore_banks[i].gpio_leveldetect0,
+				bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+		__raw_writel(gpio_restore_banks[i].gpio_leveldetect1,
+				bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+		__raw_writel(gpio_restore_banks[i].gpio_risingdetect,
+				bank->base + OMAP24XX_GPIO_RISINGDETECT);
+		__raw_writel(gpio_restore_banks[i].gpio_fallingdetect,
+				bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+		__raw_writel(gpio_restore_banks[i].gpio_dataout,
+				bank->base + OMAP24XX_GPIO_DATAOUT);
+		__raw_writel(gpio_restore_banks[i].gpio_setwkuena,
+				bank->base + OMAP24XX_GPIO_SETWKUENA);
+		__raw_writel(gpio_restore_banks[i].gpio_setdataout,
+				bank->base + OMAP24XX_GPIO_SETDATAOUT);
+	}
+}
+EXPORT_SYMBOL(omap_gpio_restore);
+#endif
+
 /*
  * This may get called early from board specific init
  * for boards that have interrupts routed via FPGA.

index 003c08e..489add6 100644
@@ -36,6 +36,8 @@ extern struct sys_timer omap_timer;
 extern void omap_serial_init(void);
 extern void omap_serial_enable_clocks(int enable);
 extern int omap_serial_can_sleep(void);
+extern void omap_gpio_save(void);
+extern void omap_gpio_restore(void);
 extern void omap_serial_fclk_mask(u32 *f1, u32 *f2);
 void omap_serial_check_wakeup(void);
 #ifdef CONFIG_I2C_OMAP

index d06146d..99ecd75 100644
@@ -26,6 +26,8 @@
 #include <asm/arch/pm.h>
 #include <asm/arch/prcm.h>
 #include <asm/arch/powerdomain.h>
+#include <asm/arch/clockdomain.h>
+#include <asm/arch/gpio.h>
 #include "cpuidle34xx.h"
 
 #ifdef CONFIG_CPU_IDLE

@@ -35,6 +37,8 @@ struct omap3_processor_cx current_cx_state;
 
 static int omap3_idle_bm_check(void)
 {
+	if (!omap3_can_sleep())
+		return 1;
 	return 0;
 }
 

@@ -46,34 +50,82 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 {
 	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
 	struct timespec ts_preidle, ts_postidle, ts_idle;
-	struct powerdomain *mpu_pd;
+	struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
+	int per_pwrst, neon_pwrst;
 
 	current_cx_state = *cx;
 
-	/* Used to keep track of the total time in idle */
-	getnstimeofday(&ts_preidle);
-
-
 	if (cx->type == OMAP3_STATE_C0) {
 		/* Do nothing for C0, not even a wfi */
 		return 0;
 	}
 
+	/* Used to keep track of the total time in idle */
+	getnstimeofday(&ts_preidle);
+
 	mpu_pd = pwrdm_lookup("mpu_pwrdm");
+	core_pd = pwrdm_lookup("core_pwrdm");
+	per_pd = pwrdm_lookup("per_pwrdm");
+	neon_pd = pwrdm_lookup("neon_pwrdm");
+
+	/* Reset previous power state registers */
+	pwrdm_clear_all_prev_pwrst(mpu_pd);
+	pwrdm_clear_all_prev_pwrst(neon_pd);
+	pwrdm_clear_all_prev_pwrst(core_pd);
+	pwrdm_clear_all_prev_pwrst(per_pd);
+
+	if (omap_irq_pending())
+		return 0;
+
+	per_pwrst = pwrdm_read_pwrst(per_pd);
+	neon_pwrst = pwrdm_read_pwrst(neon_pd);
+
 	/* Program MPU to target state */
-	if (cx->mpu_state < PWRDM_POWER_ON)
+	if (cx->mpu_state < PWRDM_POWER_ON) {
+		if (neon_pwrst == PWRDM_POWER_ON)
+			pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
 		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
+	}
+
+	/* Program CORE and PER to target state */
+	if (cx->core_state < PWRDM_POWER_ON) {
+		if (per_pwrst == PWRDM_POWER_ON) {
+			omap2_gpio_prepare_for_retention();
+			per_gpio_clk_disable();
+			omap_serial_enable_clocks(0);
+		}
+		pwrdm_set_next_pwrst(core_pd, cx->core_state);
+	}
 
 	/* Execute ARM wfi */
 	omap_sram_idle();
 
-	/* Program MPU to ON */
-	if (cx->mpu_state < PWRDM_POWER_ON)
+	/* Program MPU/NEON to ON */
+	if (cx->mpu_state < PWRDM_POWER_ON) {
+		if (neon_pwrst == PWRDM_POWER_ON)
+			pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
 		pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
+	}
+
+	if (cx->core_state < PWRDM_POWER_ON) {
+		if (per_pwrst == PWRDM_POWER_ON) {
+			omap_serial_enable_clocks(1);
+			per_gpio_clk_enable();
+			omap2_gpio_resume_after_retention();
+		}
+		pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
+	}
+
+	pr_debug("MPU prev st:%x,NEON prev st:%x\n",
+			       pwrdm_read_prev_pwrst(mpu_pd),
+			       pwrdm_read_prev_pwrst(neon_pd));
+	pr_debug("PER prev st:%x,CORE prev st:%x\n",
+			       pwrdm_read_prev_pwrst(per_pd),
+			       pwrdm_read_prev_pwrst(core_pd));
 
 	getnstimeofday(&ts_postidle);
 	ts_idle = timespec_sub(ts_postidle, ts_preidle);
-	return timespec_to_ns(&ts_idle);
+	return (u32)timespec_to_ns(&ts_idle)/1000;
 }
 
 static int omap3_enter_idle_bm(struct cpuidle_device *dev,

@@ -130,7 +182,7 @@ void omap_init_power_states(void)
 	omap3_power_states[0].threshold = 0;
 	omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
 	omap3_power_states[0].core_state = PWRDM_POWER_ON;
-	omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap3_power_states[0].flags = CPUIDLE_FLAG_SHALLOW;
 
 	/* C1 . MPU WFI + Core active */
 	omap3_power_states[1].valid = 1;

@@ -140,7 +192,8 @@ void omap_init_power_states(void)
 	omap3_power_states[1].threshold = 30;
 	omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
 	omap3_power_states[1].core_state = PWRDM_POWER_ON;
-	omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
+						CPUIDLE_FLAG_SHALLOW;
 
 	/* C2 . MPU CSWR + Core active */
 	omap3_power_states[2].valid = 1;

@@ -150,7 +203,8 @@ void omap_init_power_states(void)
 	omap3_power_states[2].threshold = 300;
 	omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
 	omap3_power_states[2].core_state = PWRDM_POWER_ON;
-	omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
+						CPUIDLE_FLAG_BALANCED;
 
 	/* C3 . MPU OFF + Core active */
 	omap3_power_states[3].valid = 0;

@@ -159,18 +213,20 @@ void omap_init_power_states(void)
 	omap3_power_states[3].wakeup_latency = 1800;
 	omap3_power_states[3].threshold = 4000;
 	omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
-	omap3_power_states[3].core_state = PWRDM_POWER_RET;
-	omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap3_power_states[3].core_state = PWRDM_POWER_ON;
+	omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
+			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
 
 	/* C4 . MPU CSWR + Core CSWR*/
-	omap3_power_states[4].valid = 0;
+	omap3_power_states[4].valid = 1;
 	omap3_power_states[4].type = OMAP3_STATE_C4;
 	omap3_power_states[4].sleep_latency = 2500;
 	omap3_power_states[4].wakeup_latency = 7500;
 	omap3_power_states[4].threshold = 12000;
 	omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
 	omap3_power_states[4].core_state = PWRDM_POWER_RET;
-	omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
+			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
 
 	/* C5 . MPU OFF + Core CSWR */
 	omap3_power_states[5].valid = 0;

@@ -180,7 +236,8 @@ void omap_init_power_states(void)
 	omap3_power_states[5].threshold = 15000;
 	omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
 	omap3_power_states[5].core_state = PWRDM_POWER_RET;
-	omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
+			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
 
 	/* C6 . MPU OFF + Core OFF */
 	omap3_power_states[6].valid = 0;

@@ -190,7 +247,8 @@ void omap_init_power_states(void)
 	omap3_power_states[6].threshold = 300000;
 	omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
 	omap3_power_states[6].core_state = PWRDM_POWER_OFF;
-	omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
+			CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
 }
 
 struct cpuidle_driver omap3_idle_driver = {

index ed8dc9b..46ed51e 100644
@@ -33,11 +33,13 @@
 /* Currently, we support only upto C2 */
 #define MAX_SUPPORTED_STATES 3
 
+extern unsigned short clocks_off_while_idle;
 extern void omap_sram_idle(void);
-extern int omap3_irq_pending(void);
+extern int omap_irq_pending(void);
 extern void per_gpio_clk_enable(void);
 extern void per_gpio_clk_disable(void);
-
+extern void omap_serial_enable_clocks(int enable);
+extern int omap3_can_sleep();
 struct omap3_processor_cx {
 	u8 valid;
 	u8 type;

index 8feab92..0646595 100644
@@ -61,7 +61,7 @@ static struct powerdomain *mpu_pwrdm;
 static struct clk *gpio_fcks[NUM_OF_PERGPIOS];
 
 /* Enable GPIO clocks from sleep routines if allowed */
-static void per_gpio_clk_enable(void)
+void per_gpio_clk_enable(void)
 {
 	int i;
 

@@ -72,7 +72,7 @@ static void per_gpio_clk_enable(void)
 }
 
 /* Disable GPIO clocks from sleep routines if allowed */
-static void per_gpio_clk_disable(void)
+void per_gpio_clk_disable(void)
 {
 	int i;
 

@@ -213,22 +213,8 @@ void omap_sram_idle(void)
 
 	pm_dbg_pre_suspend();
 
-	omap2_gpio_prepare_for_retention();
-
-	/* Disable GPIO clocks if allowed */
-	per_gpio_clk_disable();
-
-	/* Disable UART clocks if allowed */
-	omap_serial_enable_clocks(0);
-
 	_omap_sram_idle(NULL, save_state);
 
-	/* Enable UART clocks if allowed */
-	omap_serial_enable_clocks(1);
-
-	/* Enable GPIO clocks if allowed */
-	per_gpio_clk_enable();
-
 	omap2_gpio_resume_after_retention();
 
 	pm_dbg_post_suspend();

@@ -273,7 +259,7 @@ static int omap3_fclks_active(void)
 	return 0;
 }
 
-static int omap3_can_sleep(void)
+int omap3_can_sleep(void)
 {
 	if (!enable_dyn_sleep)
 		return 0;

@@ -361,8 +347,17 @@ static void omap3_pm_idle(void)
 	if (omap_irq_pending())
 		goto out;
 
+	omap2_gpio_prepare_for_retention();
+
+	omap_serial_enable_clocks(0);
+	per_gpio_clk_disable();
+
 	omap_sram_idle();
 
+	omap_serial_enable_clocks(1);
+	per_gpio_clk_enable();
+
+	omap2_gpio_resume_after_retention();
 out:
 	local_fiq_enable();
 	local_irq_enable();

@@ -395,8 +390,17 @@ static int omap3_pm_suspend(void)
 			goto restore;
 	}
 
+	omap2_gpio_prepare_for_retention();
+
+	omap_serial_enable_clocks(0);
+	per_gpio_clk_disable();
+
 	omap_sram_idle();
 
+	omap_serial_enable_clocks(1);
+	per_gpio_clk_enable();
+
+	omap2_gpio_resume_after_retention();
 restore:
 	/* Restore next_pwrsts */
 	list_for_each_entry(pwrst, &pwrst_list, node) {

index ee58873..a02da6d 100644
@@ -28,7 +28,382 @@
 #include <asm/arch/powerdomain.h>
 #include <asm/arch/clockdomain.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/gpmc.h>
+#include <asm/arch/control.h>
+#include <linux/sched.h>
 #include "cpuidle34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-34xx.h"
+#include "prm.h"
+#include "pm.h"
+#include "clock34xx.h"
+
+static int padconf_saved;
+void omap3_save_prcm_ctx(void)
+{
+	prcm_sleep_save[1] = omap_readl(INTC_MIR_0);
+	prcm_sleep_save[2] = omap_readl(INTC_MIR_1);
+	prcm_sleep_save[3] = omap_readl(INTC_MIR_2);
+	prcm_sleep_save[4] = omap_readl(CONTROL_PADCONF_SYS_NIRQ);
+	prcm_sleep_save[5] = omap_readl(OMAP34XX_GPIO1_IRQENABLE1);
+	prcm_sleep_save[6] = omap_readl(OMAP34XX_GPIO1_WAKEUPEN);
+	prcm_sleep_save[7] = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
+	prcm_sleep_save[8] = __raw_readl(OMAP3430_CM_SYSCONFIG);
+	prcm_sleep_save[9] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
+	prcm_sleep_save[10] = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+	prcm_sleep_save[11] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
+	prcm_sleep_save[12] = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
+	prcm_sleep_save[13] = cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
+	prcm_sleep_save[14] = cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
+	prcm_sleep_save[15] = cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
+	prcm_sleep_save[16] = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
+	prcm_sleep_save[17] = cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
+	prcm_sleep_save[18] = __raw_readl(OMAP3430_CM_POLCTRL);
+	prcm_sleep_save[19] = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
+	prcm_sleep_save[20] = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+	prcm_sleep_save[21] = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+	prcm_sleep_save[22] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
+	prcm_sleep_save[23] = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
+	prcm_sleep_save[24] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
+	prcm_sleep_save[25] = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
+	prcm_sleep_save[26] = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
+	prcm_sleep_save[27] = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+							      CM_FCLKEN);
+	prcm_sleep_save[28] = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
+	prcm_sleep_save[29] = cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
+	prcm_sleep_save[30] = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
+	prcm_sleep_save[31] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
+	prcm_sleep_save[32] = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
+	prcm_sleep_save[33] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
+	prcm_sleep_save[34] = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
+	prcm_sleep_save[35] = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
+	prcm_sleep_save[36] = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+							      CM_ICLKEN);
+	prcm_sleep_save[37] = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
+	prcm_sleep_save[38] = cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
+	prcm_sleep_save[39] = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+	prcm_sleep_save[40] = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
+	prcm_sleep_save[41] = cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
+	prcm_sleep_save[42] = cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
+	prcm_sleep_save[43] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+							      CM_CLKSTCTRL);
+	prcm_sleep_save[44] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
+	prcm_sleep_save[45] = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
+	prcm_sleep_save[46] = cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
+	prcm_sleep_save[47] = cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
+	prcm_sleep_save[48] = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+							      CM_CLKSTCTRL);
+	prcm_sleep_save[49] = cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
+	prcm_sleep_save[50] = cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
+	prcm_sleep_save[51] = cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
+	prcm_sleep_save[52] = cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
+	prcm_sleep_save[53] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
+	prcm_sleep_save[54] = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
+	prcm_sleep_save[55] = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+	prcm_sleep_save[56] = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+							      CM_AUTOIDLE);
+	prcm_sleep_save[57] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+						      OMAP3430_CM_SLEEPDEP);
+	prcm_sleep_save[58] = cm_read_mod_reg(OMAP3430_DSS_MOD,
+						      OMAP3430_CM_SLEEPDEP);
+	prcm_sleep_save[59] = cm_read_mod_reg(OMAP3430_CAM_MOD,
+						      OMAP3430_CM_SLEEPDEP);
+	prcm_sleep_save[60] = cm_read_mod_reg(OMAP3430_PER_MOD,
+						      OMAP3430_CM_SLEEPDEP);
+	prcm_sleep_save[61] = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+						      OMAP3430_CM_SLEEPDEP);
+	prcm_sleep_save[62] = __raw_readl(OMAP3430_CM_CLKOUT_CTRL);
+	prcm_sleep_save[63] = __raw_readl(OMAP3430_PRM_CLKOUT_CTRL);
+	prcm_sleep_save[64] = prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
+	prcm_sleep_save[65] = prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
+	prcm_sleep_save[66] = prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
+	prcm_sleep_save[67] = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
+	prcm_sleep_save[68] = prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
+	prcm_sleep_save[69] = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+							       PM_WKDEP);
+	prcm_sleep_save[70] = prm_read_mod_reg(CORE_MOD,
+					      OMAP3430_PM_MPUGRPSEL1);
+	prcm_sleep_save[71] = prm_read_mod_reg(OMAP3430_IVA2_MOD,
+					      OMAP3430_PM_IVAGRPSEL1);
+	prcm_sleep_save[72] = prm_read_mod_reg(CORE_MOD,
+					      OMAP3430ES2_PM_MPUGRPSEL3);
+	prcm_sleep_save[73] = prm_read_mod_reg(CORE_MOD,
+					      OMAP3430ES2_PM_IVAGRPSEL3);
+	prcm_sleep_save[74] = prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
+	prcm_sleep_save[75] = prm_read_mod_reg(WKUP_MOD,
+					      OMAP3430_PM_IVAGRPSEL);
+	prcm_sleep_save[76] = prm_read_mod_reg(OMAP3430_PER_MOD,
+					      OMAP3430_PM_MPUGRPSEL);
+	prcm_sleep_save[77] = prm_read_mod_reg(OMAP3430_PER_MOD,
+					      OMAP3430_PM_IVAGRPSEL);
+	prcm_sleep_save[78] = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+	return;
+}
+
+void omap3_restore_prcm_ctx(void)
+{
+	omap_writel(prcm_sleep_save[1], INTC_MIR_0);
+	omap_writel(prcm_sleep_save[2], INTC_MIR_1);
+	omap_writel(prcm_sleep_save[3], INTC_MIR_2);
+	omap_writel(prcm_sleep_save[4], CONTROL_PADCONF_SYS_NIRQ);
+	omap_writel(prcm_sleep_save[5], OMAP34XX_GPIO1_IRQENABLE1);
+	omap_writel(prcm_sleep_save[6], OMAP34XX_GPIO1_WAKEUPEN);
+	cm_write_mod_reg(prcm_sleep_save[7], OMAP3430_IVA2_MOD, CM_CLKSEL2);
+	__raw_writel(prcm_sleep_save[8], OMAP3430_CM_SYSCONFIG);
+	cm_write_mod_reg(prcm_sleep_save[9], OMAP3430ES2_SGX_MOD, CM_CLKSEL);
+	cm_write_mod_reg(prcm_sleep_save[10], WKUP_MOD, CM_CLKSEL);
+	cm_write_mod_reg(prcm_sleep_save[11], OMAP3430_DSS_MOD, CM_CLKSEL);
+	cm_write_mod_reg(prcm_sleep_save[12], OMAP3430_CAM_MOD, CM_CLKSEL);
+	cm_write_mod_reg(prcm_sleep_save[13], OMAP3430_PER_MOD, CM_CLKSEL);
+	cm_write_mod_reg(prcm_sleep_save[14], OMAP3430_EMU_MOD, CM_CLKSEL1);
+	cm_write_mod_reg(prcm_sleep_save[15], OMAP3430_EMU_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[16], PLL_MOD, CM_AUTOIDLE2);
+	cm_write_mod_reg(prcm_sleep_save[17], PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
+	__raw_writel(prcm_sleep_save[18], OMAP3430_CM_POLCTRL);
+	cm_write_mod_reg(prcm_sleep_save[19], OMAP3430_IVA2_MOD, CM_FCLKEN);
+	cm_write_mod_reg(prcm_sleep_save[20], CORE_MOD, CM_FCLKEN1);
+	cm_write_mod_reg(prcm_sleep_save[21], CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+	cm_write_mod_reg(prcm_sleep_save[22], OMAP3430ES2_SGX_MOD, CM_FCLKEN);
+	cm_write_mod_reg(prcm_sleep_save[23], WKUP_MOD, CM_FCLKEN);
+	cm_write_mod_reg(prcm_sleep_save[24], OMAP3430_DSS_MOD, CM_FCLKEN);
+	cm_write_mod_reg(prcm_sleep_save[25], OMAP3430_CAM_MOD, CM_FCLKEN);
+	cm_write_mod_reg(prcm_sleep_save[26], OMAP3430_PER_MOD, CM_FCLKEN);
+	cm_write_mod_reg(prcm_sleep_save[27], OMAP3430ES2_USBHOST_MOD,
+							       CM_FCLKEN);
+	cm_write_mod_reg(prcm_sleep_save[28], CORE_MOD, CM_ICLKEN1);
+	cm_write_mod_reg(prcm_sleep_save[29], CORE_MOD, CM_ICLKEN2);
+	cm_write_mod_reg(prcm_sleep_save[30], CORE_MOD, CM_ICLKEN3);
+	cm_write_mod_reg(prcm_sleep_save[31], OMAP3430ES2_SGX_MOD, CM_ICLKEN);
+	cm_write_mod_reg(prcm_sleep_save[32], WKUP_MOD, CM_ICLKEN);
+	cm_write_mod_reg(prcm_sleep_save[33], OMAP3430_DSS_MOD, CM_ICLKEN);
+	cm_write_mod_reg(prcm_sleep_save[34], OMAP3430_CAM_MOD, CM_ICLKEN);
+	cm_write_mod_reg(prcm_sleep_save[35], OMAP3430_PER_MOD, CM_ICLKEN);
+	cm_write_mod_reg(prcm_sleep_save[36], OMAP3430ES2_USBHOST_MOD,
+								CM_ICLKEN);
+	cm_write_mod_reg(prcm_sleep_save[37], OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
+	cm_write_mod_reg(prcm_sleep_save[38], MPU_MOD, CM_AUTOIDLE2);
+	cm_write_mod_reg(prcm_sleep_save[39], PLL_MOD, CM_AUTOIDLE);
+	cm_write_mod_reg(prcm_sleep_save[40], OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[41], MPU_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[42], CORE_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[43], OMAP3430ES2_SGX_MOD,
+						       CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[44], OMAP3430_DSS_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[45], OMAP3430_CAM_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[46], OMAP3430_PER_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[47], OMAP3430_NEON_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[48], OMAP3430ES2_USBHOST_MOD,
+							       CM_CLKSTCTRL);
+	cm_write_mod_reg(prcm_sleep_save[49], CORE_MOD, CM_AUTOIDLE1);
+	cm_write_mod_reg(prcm_sleep_save[50], CORE_MOD, CM_AUTOIDLE2);
+	cm_write_mod_reg(prcm_sleep_save[51], CORE_MOD, CM_AUTOIDLE3);
+	cm_write_mod_reg(prcm_sleep_save[52], WKUP_MOD, CM_AUTOIDLE);
+	cm_write_mod_reg(prcm_sleep_save[53], OMAP3430_DSS_MOD, CM_AUTOIDLE);
+	cm_write_mod_reg(prcm_sleep_save[54], OMAP3430_CAM_MOD, CM_AUTOIDLE);
+	cm_write_mod_reg(prcm_sleep_save[55], OMAP3430_PER_MOD, CM_AUTOIDLE);
+	cm_write_mod_reg(prcm_sleep_save[56], OMAP3430ES2_USBHOST_MOD,
+							       CM_AUTOIDLE);
+	cm_write_mod_reg(prcm_sleep_save[57], OMAP3430ES2_SGX_MOD,
+						       OMAP3430_CM_SLEEPDEP);
+	cm_write_mod_reg(prcm_sleep_save[58], OMAP3430_DSS_MOD,
+						       OMAP3430_CM_SLEEPDEP);
+	cm_write_mod_reg(prcm_sleep_save[59], OMAP3430_CAM_MOD,
+						       OMAP3430_CM_SLEEPDEP);
+	cm_write_mod_reg(prcm_sleep_save[60], OMAP3430_PER_MOD,
+						       OMAP3430_CM_SLEEPDEP);
+	cm_write_mod_reg(prcm_sleep_save[61], OMAP3430ES2_USBHOST_MOD,
+						       OMAP3430_CM_SLEEPDEP);
+	__raw_writel(prcm_sleep_save[62], OMAP3430_CM_CLKOUT_CTRL);
+	__raw_writel(prcm_sleep_save[63], OMAP3430_PRM_CLKOUT_CTRL);
+	prm_write_mod_reg(prcm_sleep_save[64], OMAP3430ES2_SGX_MOD, PM_WKDEP);
+	prm_write_mod_reg(prcm_sleep_save[65], OMAP3430_DSS_MOD, PM_WKDEP);
+	prm_write_mod_reg(prcm_sleep_save[66], OMAP3430_CAM_MOD, PM_WKDEP);
+	prm_write_mod_reg(prcm_sleep_save[67], OMAP3430_PER_MOD, PM_WKDEP);
+	prm_write_mod_reg(prcm_sleep_save[68], OMAP3430_NEON_MOD, PM_WKDEP);
+	prm_write_mod_reg(prcm_sleep_save[69], OMAP3430ES2_USBHOST_MOD,
+							       PM_WKDEP);
+	prm_write_mod_reg(prcm_sleep_save[70], CORE_MOD,
+					       OMAP3430_PM_MPUGRPSEL1);
+	prm_write_mod_reg(prcm_sleep_save[71], OMAP3430_IVA2_MOD,
+					       OMAP3430_PM_IVAGRPSEL1);
+	prm_write_mod_reg(prcm_sleep_save[72], CORE_MOD,
+					       OMAP3430ES2_PM_MPUGRPSEL3);
+	prm_write_mod_reg(prcm_sleep_save[73], CORE_MOD,
+					       OMAP3430ES2_PM_IVAGRPSEL3);
+	prm_write_mod_reg(prcm_sleep_save[74], WKUP_MOD,
+					       OMAP3430_PM_MPUGRPSEL);
+	prm_write_mod_reg(prcm_sleep_save[75], WKUP_MOD,
+					       OMAP3430_PM_IVAGRPSEL);
+	prm_write_mod_reg(prcm_sleep_save[76], OMAP3430_PER_MOD,
+					       OMAP3430_PM_MPUGRPSEL);
+	prm_write_mod_reg(prcm_sleep_save[77], OMAP3430_PER_MOD,
+					       OMAP3430_PM_IVAGRPSEL);
+	prm_write_mod_reg(prcm_sleep_save[78], WKUP_MOD, PM_WKEN);
+	return;
+}
+
+static void omap_save_intc_ctx(void)
+{
+	int ind = 0;
+	intc_context.sysconfig = omap_readl(INTCPS_SYSCONFIG);
+	intc_context.protection =  omap_readl(INTCPS_PROTECTION);
+	intc_context.idle = omap_readl(INTCPS_IDLE);
+	intc_context.threshold = omap_readl(INTCPS_THRESHOLD);
+	for (ind = 0; ind < 96; ind++)
+	       intc_context.ilr[ind] =
+		       omap_readl(INTC_BASE + (0x100 + 0x4*ind));
+	/* MIRs are saved and restore with other PRCM registers */
+}
+
+static void omap_restore_intc_ctx(void)
+{
+	int ind = 0;
+	omap_writel(intc_context.sysconfig, INTCPS_SYSCONFIG);
+	omap_writel(intc_context.protection, INTCPS_PROTECTION);
+	omap_writel(intc_context.idle, INTCPS_IDLE);
+	omap_writel(intc_context.threshold, INTCPS_THRESHOLD);
+	for (ind = 0; ind < 96; ind++)
+	       omap_writel(intc_context.ilr[ind],
+		       INTC_BASE + (0x100 + 0x4*ind));
+	/* MIRs are saved and restore with other PRCM registers */
+}
+
+static void omap_save_control_ctx(void)
+{
+	control_ctx.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
+	control_ctx.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	control_ctx.mem_dftrw0 = omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
+	control_ctx.mem_dftrw1 = omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
+	control_ctx.msuspendmux_0 =
+		       omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
+	control_ctx.msuspendmux_1 =
+		       omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
+	control_ctx.msuspendmux_2 =
+		       omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
+	control_ctx.msuspendmux_3 =
+		       omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
+	control_ctx.msuspendmux_4 =
+		       omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
+	control_ctx.msuspendmux_5 =
+		       omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
+	control_ctx.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
+	control_ctx.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
+	control_ctx.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
+	control_ctx.iva2_bootaddr =
+		       omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
+	control_ctx.iva2_bootmod =
+		       omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
+	control_ctx.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_0);
+	control_ctx.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_1);
+	control_ctx.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_2);
+	control_ctx.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_3);
+	control_ctx.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_4);
+	control_ctx.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_5);
+	control_ctx.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_6);
+	control_ctx.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_7);
+	control_ctx.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS_8);
+	control_ctx.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
+	control_ctx.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
+	control_ctx.dss_dpll_spreading =
+	       omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
+	control_ctx.core_dpll_spreading =
+	       omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
+	control_ctx.per_dpll_spreading =
+	       omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
+	control_ctx.usbhost_dpll_spreading =
+	       omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
+	control_ctx.pbias_lite = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
+	control_ctx.temp_sensor = omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
+	control_ctx.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
+	control_ctx.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
+	control_ctx.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
+	return;
+}
+
+static void omap_restore_control_ctx(void)
+{
+	omap_ctrl_writel(control_ctx.sysconfig, OMAP2_CONTROL_SYSCONFIG);
+	omap_ctrl_writel(control_ctx.devconf0, OMAP2_CONTROL_DEVCONF0);
+	omap_ctrl_writel(control_ctx.mem_dftrw0, OMAP343X_CONTROL_MEM_DFTRW0);
+	omap_ctrl_writel(control_ctx.mem_dftrw1, OMAP343X_CONTROL_MEM_DFTRW1);
+	omap_ctrl_writel(control_ctx.msuspendmux_0,
+					       OMAP2_CONTROL_MSUSPENDMUX_0);
+	omap_ctrl_writel(control_ctx.msuspendmux_1,
+					       OMAP2_CONTROL_MSUSPENDMUX_1);
+	omap_ctrl_writel(control_ctx.msuspendmux_2,
+					       OMAP2_CONTROL_MSUSPENDMUX_2);
+	omap_ctrl_writel(control_ctx.msuspendmux_3,
+					       OMAP2_CONTROL_MSUSPENDMUX_3);
+	omap_ctrl_writel(control_ctx.msuspendmux_4,
+					       OMAP2_CONTROL_MSUSPENDMUX_4);
+	omap_ctrl_writel(control_ctx.msuspendmux_5,
+					       OMAP2_CONTROL_MSUSPENDMUX_5);
+	omap_ctrl_writel(control_ctx.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
+	omap_ctrl_writel(control_ctx.devconf1, OMAP343X_CONTROL_DEVCONF1);
+	omap_ctrl_writel(control_ctx.csirxfe, OMAP343X_CONTROL_CSIRXFE);
+	omap_ctrl_writel(control_ctx.iva2_bootaddr,
+					       OMAP343X_CONTROL_IVA2_BOOTADDR);
+	omap_ctrl_writel(control_ctx.iva2_bootmod,
+					       OMAP343X_CONTROL_IVA2_BOOTMOD);
+	omap_ctrl_writel(control_ctx.debobs_0, OMAP343X_CONTROL_DEBOBS_0);
+	omap_ctrl_writel(control_ctx.debobs_1, OMAP343X_CONTROL_DEBOBS_1);
+	omap_ctrl_writel(control_ctx.debobs_2, OMAP343X_CONTROL_DEBOBS_2);
+	omap_ctrl_writel(control_ctx.debobs_3, OMAP343X_CONTROL_DEBOBS_3);
+	omap_ctrl_writel(control_ctx.debobs_4, OMAP343X_CONTROL_DEBOBS_4);
+	omap_ctrl_writel(control_ctx.debobs_5, OMAP343X_CONTROL_DEBOBS_5);
+	omap_ctrl_writel(control_ctx.debobs_6, OMAP343X_CONTROL_DEBOBS_6);
+	omap_ctrl_writel(control_ctx.debobs_7, OMAP343X_CONTROL_DEBOBS_7);
+	omap_ctrl_writel(control_ctx.debobs_8, OMAP343X_CONTROL_DEBOBS_8);
+	omap_ctrl_writel(control_ctx.prog_io0, OMAP343X_CONTROL_PROG_IO0);
+	omap_ctrl_writel(control_ctx.prog_io1, OMAP343X_CONTROL_PROG_IO1);
+	omap_ctrl_writel(control_ctx.dss_dpll_spreading,
+			       OMAP343X_CONTROL_DSS_DPLL_SPREADING);
+	omap_ctrl_writel(control_ctx.core_dpll_spreading,
+			       OMAP343X_CONTROL_CORE_DPLL_SPREADING);
+	omap_ctrl_writel(control_ctx.per_dpll_spreading,
+			       OMAP343X_CONTROL_PER_DPLL_SPREADING);
+	omap_ctrl_writel(control_ctx.usbhost_dpll_spreading,
+			       OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
+	omap_ctrl_writel(control_ctx.pbias_lite, OMAP343X_CONTROL_PBIAS_LITE);
+	omap_ctrl_writel(control_ctx.temp_sensor, OMAP343X_CONTROL_TEMP_SENSOR);
+	omap_ctrl_writel(control_ctx.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
+	omap_ctrl_writel(control_ctx.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
+	omap_ctrl_writel(control_ctx.csi, OMAP343X_CONTROL_CSI);
+	return;
+}
+
+void omap3_save_core_ctx(void)
+{
+	u32 control_padconf_off;
+
+	if (!padconf_saved) {
+	       /* Save the padconf registers */
+	       control_padconf_off = omap_readl(CONTROL_PADCONF_OFF);
+	       control_padconf_off |= 2;
+	       omap_writel(control_padconf_off, CONTROL_PADCONF_OFF);
+	       /* wait for the save to complete */
+	       while (!omap_readl(CONTROL_GENERAL_PURPOSE_STATUS) & 0x1);
+	       padconf_saved = 1;
+	}
+	/* Save the Interrupt controller context */
+	omap_save_intc_ctx();
+	/* Save the GPMC context */
+	omap_save_gpmc_ctx();
+	/* Save the system control module context, padconf already save above*/
+	omap_save_control_ctx();
+}
+
+void omap3_restore_core_ctx(void)
+{
+	/* Restore the control module context, padconf restored by h/w */
+	omap_restore_control_ctx();
+	/* Restore the GPMC context */
+	omap_restore_gpmc_ctx();
+	/* Restore the interrupt controller context */
+	omap_restore_intc_ctx();
+	padconf_saved = 0;
+}
 
 #ifdef CONFIG_CPU_IDLE
 

@@ -42,6 +417,8 @@ static int omap3_idle_bm_check(void)
 	return 0;
 }
 
+
+int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 /* omap3_enter_idle - Programs OMAP3 to enter the specified state.
  * returns the total time during which the system was idle.
  */

@@ -50,8 +427,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 {
 	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
 	struct timespec ts_preidle, ts_postidle, ts_idle;
-	struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
-	int per_pwrst, neon_pwrst;
+	struct powerdomain *mpu_pd, *core_pd;
 
 	current_cx_state = *cx;
 

@@ -60,79 +436,37 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 		return 0;
 	}
 
+	local_irq_disable();
+	local_fiq_disable();
+
 	/* Used to keep track of the total time in idle */
 	getnstimeofday(&ts_preidle);
 
+	if (cx->type > OMAP3_STATE_C1)
+		sched_clock_idle_sleep_event(); /* about to enter deep idle */
+
 	mpu_pd = pwrdm_lookup("mpu_pwrdm");
 	core_pd = pwrdm_lookup("core_pwrdm");
-	per_pd = pwrdm_lookup("per_pwrdm");
-	neon_pd = pwrdm_lookup("neon_pwrdm");
 
-	/* Reset previous power state registers */
-	pwrdm_clear_all_prev_pwrst(mpu_pd);
-	pwrdm_clear_all_prev_pwrst(neon_pd);
-	pwrdm_clear_all_prev_pwrst(core_pd);
-	pwrdm_clear_all_prev_pwrst(per_pd);
+	set_pwrdm_state(mpu_pd, cx->mpu_state);
+	set_pwrdm_state(core_pd, cx->core_state);
 
 	if (omap_irq_pending())
-		return 0;
-
-	per_pwrst = pwrdm_read_pwrst(per_pd);
-	neon_pwrst = pwrdm_read_pwrst(neon_pd);
-
-	/* Program MPU to target state */
-	if (cx->mpu_state < PWRDM_POWER_ON) {
-		if (neon_pwrst == PWRDM_POWER_ON) {
-			if (cx->mpu_state == PWRDM_POWER_RET)
-				pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
-			else if (cx->mpu_state == PWRDM_POWER_OFF)
-				pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
-		}
-		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
-	}
-
-	/* Program CORE and PER to target state */
-	if (cx->core_state < PWRDM_POWER_ON) {
-		if (per_pwrst == PWRDM_POWER_ON) {
-			omap2_gpio_prepare_for_retention();
-			per_gpio_clk_disable();
-			omap_serial_enable_clocks(0);
-		}
-		pwrdm_set_next_pwrst(core_pd, cx->core_state);
-	}
-
-	*(scratchpad_restore_addr) = restore_pointer_address;
+		goto return_sleep_time;
 
 	/* Execute ARM wfi */
 	omap_sram_idle();
 
-	*(scratchpad_restore_addr) = 0x0;
-
-	/* Program MPU/NEON to ON */
-	if (cx->mpu_state < PWRDM_POWER_ON) {
-		if (neon_pwrst == PWRDM_POWER_ON)
-			pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
-		pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
-	}
+return_sleep_time:
+	getnstimeofday(&ts_postidle);
+	ts_idle = timespec_sub(ts_postidle, ts_preidle);
 
-	if (cx->core_state < PWRDM_POWER_ON) {
-		if (per_pwrst == PWRDM_POWER_ON) {
-			omap_serial_enable_clocks(1);
-			per_gpio_clk_enable();
-			omap2_gpio_resume_after_retention();
-		}
-		pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
-	}
+	if (cx->type > OMAP3_STATE_C1)
+		sched_clock_idle_wakeup_event(timespec_to_ns(&ts_idle));
 
-	pr_debug("MPU prev st:%x,NEON prev st:%x\n",
-			       pwrdm_read_prev_pwrst(mpu_pd),
-			       pwrdm_read_prev_pwrst(neon_pd));
-	pr_debug("PER prev st:%x,CORE prev st:%x\n",
-			       pwrdm_read_prev_pwrst(per_pd),
-			       pwrdm_read_prev_pwrst(core_pd));
+	local_irq_enable();
+	local_fiq_enable();
 
-	getnstimeofday(&ts_postidle);
-	ts_idle = timespec_sub(ts_postidle, ts_preidle);
 	return (u32)timespec_to_ns(&ts_idle)/1000;
 }
 

@@ -143,25 +477,28 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 	int i, j;
 
 	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
-
-		/* Find current state in list */
-		for (i = 0; i < OMAP3_MAX_STATES; i++)
-			if (state == &dev->states[i])
-				break;
-		BUG_ON(i == OMAP3_MAX_STATES);
-
-		/* Back up to non 'CHECK_BM' state */
-		for (j = i - 1;  j > 0; j--) {
-			struct cpuidle_state *s = &dev->states[j];
-
-			if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
-				new_state = s;
-				break;
+		if (dev->safe_state)
+			return dev->safe_state->enter(dev, dev->safe_state);
+		else {
+			/* Find current state in list */
+			for (i = 0; i < OMAP3_MAX_STATES; i++)
+				if (state == &dev->states[i])
+					break;
+			BUG_ON(i == OMAP3_MAX_STATES);
+
+			/* Back up to non 'CHECK_BM' state */
+			for (j = i - 1;  j >= 0; j--) {
+				struct cpuidle_state *s = &dev->states[j];
+
+				if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
+					new_state = s;
+					break;
+				}
 			}
+			pr_debug("%s: Bus activity: Entering %s\
+				(instead of %s)\n", __func__,
+				 new_state->name, state->name);
 		}
-
-		pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",
-			__func__, new_state->name, state->name);
 	}
 
 	return omap3_enter_idle(dev, new_state ? : state);

@@ -183,79 +520,79 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 void omap_init_power_states(void)
 {
 	/* C0 . System executing code */
-	omap3_power_states[0].valid = 1;
-	omap3_power_states[0].type = OMAP3_STATE_C0;
-	omap3_power_states[0].sleep_latency = 0;
-	omap3_power_states[0].wakeup_latency = 0;
-	omap3_power_states[0].threshold = 0;
-	omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
-	omap3_power_states[0].core_state = PWRDM_POWER_ON;
-	omap3_power_states[0].flags = CPUIDLE_FLAG_SHALLOW;
+	omap3_power_states[OMAP3_STATE_C0].valid = 1;
+	omap3_power_states[OMAP3_STATE_C0].type = OMAP3_STATE_C0;
+	omap3_power_states[OMAP3_STATE_C0].sleep_latency = 0;
+	omap3_power_states[OMAP3_STATE_C0].wakeup_latency = 0;
+	omap3_power_states[OMAP3_STATE_C0].threshold = 0;
+	omap3_power_states[OMAP3_STATE_C0].mpu_state = PWRDM_POWER_ON;
+	omap3_power_states[OMAP3_STATE_C0].core_state = PWRDM_POWER_ON;
+	omap3_power_states[OMAP3_STATE_C0].flags = CPUIDLE_FLAG_SHALLOW;
 
 	/* C1 . MPU WFI + Core active */
-	omap3_power_states[1].valid = 1;
-	omap3_power_states[1].type = OMAP3_STATE_C1;
-	omap3_power_states[1].sleep_latency = 10;
-	omap3_power_states[1].wakeup_latency = 10;
-	omap3_power_states[1].threshold = 30;
-	omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
-	omap3_power_states[1].core_state = PWRDM_POWER_ON;
-	omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
+	omap3_power_states[OMAP3_STATE_C1].valid = 1;
+	omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
+	omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10;
+	omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 10;
+	omap3_power_states[OMAP3_STATE_C1].threshold = 30;
+	omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
+	omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
+	omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID |
 						CPUIDLE_FLAG_SHALLOW;
 
 	/* C2 . MPU CSWR + Core active */
-	omap3_power_states[2].valid = 1;
-	omap3_power_states[2].type = OMAP3_STATE_C2;
-	omap3_power_states[2].sleep_latency = 50;
-	omap3_power_states[2].wakeup_latency = 50;
-	omap3_power_states[2].threshold = 300;
-	omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
-	omap3_power_states[2].core_state = PWRDM_POWER_ON;
-	omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
+	omap3_power_states[OMAP3_STATE_C2].valid = 1;
+	omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
+	omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50;
+	omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 50;
+	omap3_power_states[OMAP3_STATE_C2].threshold = 300;
+	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
+	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
 						CPUIDLE_FLAG_BALANCED;
 
 	/* C3 . MPU OFF + Core active */
-	omap3_power_states[3].valid = 1;
-	omap3_power_states[3].type = OMAP3_STATE_C3;
-	omap3_power_states[3].sleep_latency = 1500;
-	omap3_power_states[3].wakeup_latency = 1800;
-	omap3_power_states[3].threshold = 4000;
-	omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
-	omap3_power_states[3].core_state = PWRDM_POWER_ON;
-	omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
-			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
+	omap3_power_states[OMAP3_STATE_C3].valid = 1;
+	omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
+	omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500;
+	omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 1800;
+	omap3_power_states[OMAP3_STATE_C3].threshold = 4000;
+	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
+	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
+			CPUIDLE_FLAG_BALANCED;
 
 	/* C4 . MPU CSWR + Core CSWR*/
-	omap3_power_states[4].valid = 1;
-	omap3_power_states[4].type = OMAP3_STATE_C4;
-	omap3_power_states[4].sleep_latency = 2500;
-	omap3_power_states[4].wakeup_latency = 7500;
-	omap3_power_states[4].threshold = 12000;
-	omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
-	omap3_power_states[4].core_state = PWRDM_POWER_RET;
-	omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
+	omap3_power_states[OMAP3_STATE_C4].valid = 1;
+	omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
+	omap3_power_states[OMAP3_STATE_C4].sleep_latency = 2500;
+	omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 7500;
+	omap3_power_states[OMAP3_STATE_C4].threshold = 12000;
+	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
 			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
 
 	/* C5 . MPU OFF + Core CSWR */
-	omap3_power_states[5].valid = 1;
-	omap3_power_states[5].type = OMAP3_STATE_C5;
-	omap3_power_states[5].sleep_latency = 3000;
-	omap3_power_states[5].wakeup_latency = 8500;
-	omap3_power_states[5].threshold = 15000;
-	omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
-	omap3_power_states[5].core_state = PWRDM_POWER_RET;
-	omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
+	omap3_power_states[OMAP3_STATE_C5].valid = 1;
+	omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
+	omap3_power_states[OMAP3_STATE_C5].sleep_latency = 3000;
+	omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 8500;
+	omap3_power_states[OMAP3_STATE_C5].threshold = 15000;
+	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
 			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
 
 	/* C6 . MPU OFF + Core OFF */
-	omap3_power_states[6].valid = 0;
-	omap3_power_states[6].type = OMAP3_STATE_C6;
-	omap3_power_states[6].sleep_latency = 10000;
-	omap3_power_states[6].wakeup_latency = 30000;
-	omap3_power_states[6].threshold = 300000;
-	omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
-	omap3_power_states[6].core_state = PWRDM_POWER_OFF;
-	omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
+	omap3_power_states[OMAP3_STATE_C6].valid = 1;
+	omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
+	omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000;
+	omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000;
+	omap3_power_states[OMAP3_STATE_C6].threshold = 300000;
+	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
 			CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
 }
 

@@ -273,6 +610,7 @@ int omap3_idle_init(void)
 	struct omap3_processor_cx *cx;
 	struct cpuidle_state *state;
 	struct cpuidle_device *dev;
+	char clk_name[11];
 
 	clear_scratchpad_contents();
 	save_scratchpad_contents();

@@ -294,6 +632,8 @@ int omap3_idle_init(void)
 		state->flags = cx->flags;
 		state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
 			omap3_enter_idle_bm : omap3_enter_idle;
+		if (cx->type == OMAP3_STATE_C1)
+			dev->safe_state = state;
 		sprintf(state->name, "C%d", count+1);
 		count++;
 	}

index f2ebe68..a2036cf 100644
@@ -30,20 +30,42 @@
 #define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
 #define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
 
-/* Currently, we support only upto C2 */
-#define MAX_SUPPORTED_STATES 3
+/* Interrupt Controller registers */
+#define INTC_BASE	0x48200000
+#define INTC_MIR_0	0x48200084
+#define INTC_MIR_1	0x482000A4
+#define INTC_MIR_2	0x482000C4
+#define INTCPS_SYSCONFIG	0x48200010
+#define INTCPS_PROTECTION	0x4820004C
+#define INTCPS_IDLE	0x48200050
+#define INTCPS_THRESHOLD	0x48200068
+
+#define CONTROL_PADCONF_SYS_NIRQ	0x480021E0
+#define CONTROL_PADCONF_OFF	0x48002270
+#define CONTROL_GENERAL_PURPOSE_STATUS	0x480022F4
+
+#define OMAP34XX_GPIO1_IRQENABLE1	0x4831001c
+#define OMAP34XX_GPIO1_WAKEUPEN	0x48310020
+#define OMAP34XX_GPIO1_FALLINGDETECT	0x4831004c
 
 extern unsigned short clocks_off_while_idle;
 extern void omap_sram_idle(void);
 extern int omap_irq_pending(void);
 extern void per_gpio_clk_enable(void);
 extern void per_gpio_clk_disable(void);
-extern void omap_serial_enable_clocks(int enable);
+extern void omap_serial_enable_clocks(int enable, int unum);
 extern int omap3_can_sleep();
 extern void clear_scratchpad_contents(void);
 extern void save_scratchpad_contents(void);
 extern u32 *scratchpad_restore_addr;
 extern u32 restore_pointer_address;
+extern void omap3_save_per_ctx();
+extern void omap3_restore_per_ctx();
+extern void omap_save_uart_ctx(int);
+extern void omap_restore_uart_ctx(int);
+extern void omap3_restore_sram_ctx();
+extern int omap3_can_sleep();
+extern int omap_serial_can_sleep();
 
 struct omap3_processor_cx {
 	u8 valid;

@@ -59,5 +81,10 @@ struct omap3_processor_cx {
 void omap_init_power_states(void);
 int omap3_idle_init(void);
 
+/* TODO fix the size:100 */
+static unsigned int prcm_sleep_save[100];
+static struct int_controller_context intc_context;
+static struct control_module_context control_ctx;
+
 #endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */
 

241 lines not on this page · raw message

index 3c6418e..a344e40 100644
@@ -137,9 +137,11 @@
 
 #define OMAP3430_PM_MPUGRPSEL				0x00a4
 #define OMAP3430_PM_MPUGRPSEL1				OMAP3430_PM_MPUGRPSEL
+#define OMAP3430ES2_PM_MPUGRPSEL3			0x00f8
 
 #define OMAP3430_PM_IVAGRPSEL				0x00a8
 #define OMAP3430_PM_IVAGRPSEL1				OMAP3430_PM_IVAGRPSEL
+#define OMAP3430ES2_PM_IVAGRPSEL3			0x00f4
 
 #define OMAP3430_PM_PREPWSTST				0x00e8
 

index 879d7c1..c189cc9 100644
@@ -157,20 +157,17 @@ static void omap_serial_kick(void)
 		NSEC_PER_MSEC);
 }
 
-void omap_serial_enable_clocks(int enable)
+void omap_serial_enable_clocks(int enable, int unum)
 {
-	int i;
 	if (uart_clocks_off_while_idle == 0)
 		return;
-	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
-		if (uart_ick[i] && uart_fck[i]) {
-			if (enable) {
-				clk_enable(uart_ick[i]);
-				clk_enable(uart_fck[i]);
-			} else {
-				clk_disable(uart_ick[i]);
-				clk_disable(uart_fck[i]);
-			}
+	if (uart_ick[unum] && uart_fck[unum]) {
+		if (enable) {
+			clk_enable(uart_ick[unum]);
+			clk_enable(uart_fck[unum]);
+		} else {
+			clk_disable(uart_ick[unum]);
+			clk_disable(uart_fck[unum]);
 		}
 	}
 }

index 489add6..faba335 100644
@@ -34,7 +34,7 @@ struct sys_timer;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 extern void omap_serial_init(void);
-extern void omap_serial_enable_clocks(int enable);
+extern void omap_serial_enable_clocks(int enable, int unum);
 extern int omap_serial_can_sleep(void);
 extern void omap_gpio_save(void);
 extern void omap_gpio_restore(void);

index 9ca0e08..ef8cf12 100644
@@ -149,7 +149,27 @@
 #define OMAP343X_CONTROL_FUSE_SR	(OMAP2_CONTROL_GENERAL + 0x0130)
 #define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP343X_CONTROL_TEMP_SENSOR	(OMAP2_CONTROL_GENERAL + 0x02b4)
+#define OMAP343X_CONTROL_DEBOBS_0	(OMAP2_CONTROL_GENERAL + 0x01B0)
+#define OMAP343X_CONTROL_DEBOBS_1	(OMAP2_CONTROL_GENERAL + 0x01B4)
+#define OMAP343X_CONTROL_DEBOBS_2	(OMAP2_CONTROL_GENERAL + 0x01B8)
+#define OMAP343X_CONTROL_DEBOBS_3	(OMAP2_CONTROL_GENERAL + 0x01BC)
+#define OMAP343X_CONTROL_DEBOBS_4	(OMAP2_CONTROL_GENERAL + 0x01C0)
+#define OMAP343X_CONTROL_DEBOBS_5	(OMAP2_CONTROL_GENERAL + 0x01C4)
+#define OMAP343X_CONTROL_DEBOBS_6	(OMAP2_CONTROL_GENERAL + 0x01C8)
+#define OMAP343X_CONTROL_DEBOBS_7	(OMAP2_CONTROL_GENERAL + 0x01CC)
+#define OMAP343X_CONTROL_DEBOBS_8	(OMAP2_CONTROL_GENERAL + 0x01D0)
+#define OMAP343X_CONTROL_PROG_IO0	(OMAP2_CONTROL_GENERAL + 0x01D4)
+#define OMAP343X_CONTROL_PROG_IO1	(OMAP2_CONTROL_GENERAL + 0x01D8)
+#define OMAP343X_CONTROL_DSS_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E0)
+#define OMAP343X_CONTROL_CORE_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E4)
+#define OMAP343X_CONTROL_PER_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E8)
+#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
+#define OMAP343X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x02B0)
+#define OMAP343X_CONTROL_TEMP_SENSOR	(OMAP2_CONTROL_GENERAL + 0x02B4)
+#define OMAP343X_CONTROL_SRAMLDO4	(OMAP2_CONTROL_GENERAL + 0x02B8)
+#define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)
+#define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02b4)
+
 
 /*
  * REVISIT: This list of registers is not comprehensive - there are more

61 lines not on this page · raw message

index 853048d..9cfb77f 100644
@@ -26,6 +26,7 @@
 #include <mach/board.h>
 
 #include <mach/control.h>
+#include <mach/pm.h>
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 # include "../mach-omap2/prm.h"

@@ -75,6 +76,8 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
 					 unsigned long sram_size,
 					 unsigned long pstart_avail,
 					 unsigned long size_avail);
+extern void (*_omap_sram_idle)(u32 *addr, int save_state, int disable_clocks);
+extern void omap_push_sram_idle();
 
 /*
  * Depending on the target RAMFS firewall setup, the public usable amount of

@@ -108,6 +111,7 @@ static int is_sram_locked(void)
 		return 1; /* assume locked with no PPA or security driver */
 }
 
+
 /*
  * The amount of SRAM depends on the core type.
  * Note that we cannot try to test for SRAM here because writes

@@ -368,13 +372,14 @@ u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
  }
 
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
-void restore_sram_functions(void)
+void omap3_restore_sram_ctx(void)
 {
 	omap_sram_ceil = omap_sram_base + omap_sram_size;
 
 	_omap3_sram_configure_core_dpll =
 		omap_sram_push(omap3_sram_configure_core_dpll,
 			       omap3_sram_configure_core_dpll_sz);
+	omap_push_sram_idle();
 }
 
 int __init omap3_sram_init(void)

@@ -382,6 +387,8 @@ int __init omap3_sram_init(void)
 	_omap3_sram_configure_core_dpll =
 		omap_sram_push(omap3_sram_configure_core_dpll,
 			       omap3_sram_configure_core_dpll_sz);
+	_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
+				omap34xx_cpu_suspend_sz);
 
 	return 0;
 }

index 39aca22..aa21e12 100644
@@ -1214,6 +1214,15 @@ static inline void __stop_tx(struct uart_8250_port *p)
 		p->ier &= ~UART_IER_THRI;
 		serial_out(p, UART_IER, p->ier);
 	}
+#ifdef CONFIG_ARCH_OMAP3
+	{
+		unsigned int tmp;
+		/* Allow dynamic handshake to allow OCP bus idle. RX events
+		 * can do async wake */
+		tmp = (serial_in(p, UART_OMAP_SYSC) & 0x7) | (2 << 3);
+		serial_out(p, UART_OMAP_SYSC, tmp); /* smart-idle */
+	}
+#endif
 }
 
 static void serial8250_stop_tx(struct uart_port *port)

@@ -1261,6 +1270,17 @@ static void serial8250_start_tx(struct uart_port *port)
 		up->acr &= ~UART_ACR_TXDIS;
 		serial_icr_write(up, UART_ACR, up->acr);
 	}
+#ifdef CONFIG_ARCH_OMAP3
+	{
+		unsigned int tmp;
+		/* Disallow OCP bus idle. UART TX irqs are not seen during
+		 * bus idle. Alternative is to set kernel timer at fifo
+		 * drain rate.
+		 */
+		tmp = (serial_in(up, UART_OMAP_SYSC) & 0x7) | (1 << 3);
+		serial_out(up, UART_OMAP_SYSC, tmp); /* no-idle */
+	}
+#endif
 }
 
 static void serial8250_stop_rx(struct uart_port *port)

index a02da6d..b19d2eb 100644
@@ -431,7 +431,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 
 	current_cx_state = *cx;
 
-	if (cx->type == OMAP3_STATE_C0) {
+	if (cx->type == OMAP3_STATE_C0 || !omap_serial_can_sleep()) {
 		/* Do nothing for C0, not even a wfi */
 		return 0;
 	}

index da6eae1..42fa546 100644
@@ -398,8 +398,6 @@ int omap3_can_sleep(void)
 		return 0;
 	if (atomic_read(&sleep_block) > 0)
 		return 0;
-	if (!omap_serial_can_sleep())
-		return 0;
 	return 1;
 }
 

@@ -478,6 +476,9 @@ static void omap3_pm_idle(void)
 	if (omap_irq_pending())
 		goto out;
 
+	if (!omap_serial_can_sleep())
+		goto out;
+
 	omap2_gpio_prepare_for_retention();
 
 	omap_serial_enable_clocks(0, 0);

index 53814b6..0267959 100644
@@ -1060,10 +1060,7 @@ static void __init configure_vc(void)
 				OMAP3_PRM_VC_I2C_CFG_OFFSET);
 
 	/* Setup voltctrl and other setup times */
-
-#ifdef CONFIG_OMAP_SYSOFFMODE
-	prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET |
-			OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
+	prm_write_mod_reg(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
 			OMAP3_PRM_VOLTCTRL_OFFSET);
 
 	prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,

@@ -1078,11 +1075,6 @@ static void __init configure_vc(void)
 			OMAP3_PRM_VOLTOFFSET_OFFSET);
 	prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
 			OMAP3_PRM_VOLTSETUP2_OFFSET);
-#else
-	prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
-			OMAP3_PRM_VOLTCTRL_OFFSET);
-#endif
-
 }
 
 static int __init omap3_pm_early_init(void)

index f82b5a7..d73eee8 100644
@@ -466,13 +466,13 @@
 #define OMAP3430_VC_CMD_VAL0_ON				(0x3 << 4)
 #define OMAP3430_VC_CMD_VAL0_ONLP			(0x3 << 3)
 #define OMAP3430_VC_CMD_VAL0_RET			(0x3 << 3)
-#define OMAP3430_VC_CMD_VAL0_OFF			(0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_OFF			(0x3 << 4)
 
 /* PRM_VC_CMD_VAL_1 specific bits */
 #define OMAP3430_VC_CMD_VAL1_ON				(0xB << 2)
 #define OMAP3430_VC_CMD_VAL1_ONLP			(0x3 << 3)
 #define OMAP3430_VC_CMD_VAL1_RET			(0x3 << 3)
-#define OMAP3430_VC_CMD_VAL1_OFF			(0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_OFF			(0xB << 2)
 
 /* PRM_VC_CH_CONF */
 #define OMAP3430_CMD1					(1 << 20)

index ae324b4..d696dde 100644
@@ -465,6 +465,7 @@ err:
 	return ret;
 }
 
+#ifndef CONFIG_CPU_IDLE
 static void omap3_pm_idle(void)
 {
 	local_irq_disable();

@@ -484,6 +485,7 @@ out:
 	local_fiq_enable();
 	local_irq_enable();
 }
+#endif /* CONFIG_CPU_IDLE */
 
 static int omap3_pm_prepare(void)
 {

index 11ff573..c970a06 100644
@@ -30,6 +30,7 @@
 #include <mach/gpio.h>
 #include <mach/gpmc.h>
 #include <mach/control.h>
+#include <mach/dma.h>
 #include <linux/sched.h>
 #include "cpuidle34xx.h"
 #include "cm.h"

@@ -392,6 +393,7 @@ void omap3_save_core_ctx(void)
 	omap_save_gpmc_ctx();
 	/* Save the system control module context, padconf already save above*/
 	omap_save_control_ctx();
+	omap_dma_global_context_save();
 }
 
 void omap3_restore_core_ctx(void)

@@ -402,6 +404,7 @@ void omap3_restore_core_ctx(void)
 	omap_restore_gpmc_ctx();
 	/* Restore the interrupt controller context */
 	omap_restore_intc_ctx();
+	omap_dma_global_context_restore();
 	padconf_saved = 0;
 }
 

index eaea12a..38c57ce 100644
@@ -51,6 +51,12 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 
 static int enable_1510_mode;
 
+static struct omap_dma_global_context_registers {
+	u32 dma_irqenable_l0;
+	u32 dma_ocp_sysconfig;
+	u32 dma_gcr;
+} omap_dma_global_context;
+
 struct omap_dma_lch {
 	int next_lch;
 	int dev_id;

@@ -2291,6 +2297,26 @@ void omap_stop_lcd_dma(void)
 }
 EXPORT_SYMBOL(omap_stop_lcd_dma);
 
+void omap_dma_global_context_save(void)
+{
+	omap_dma_global_context.dma_irqenable_l0 =
+		dma_read(IRQENABLE_L0);
+	omap_dma_global_context.dma_ocp_sysconfig =
+		dma_read(OCP_SYSCONFIG);
+	omap_dma_global_context.dma_gcr = dma_read(GCR);
+}
+EXPORT_SYMBOL(omap_dma_global_context_save);
+
+void omap_dma_global_context_restore(void)
+{
+	dma_write(omap_dma_global_context.dma_gcr, GCR);
+	dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+		OCP_SYSCONFIG);
+	dma_write(omap_dma_global_context.dma_irqenable_l0,
+		IRQENABLE_L0);
+}
+EXPORT_SYMBOL(omap_dma_global_context_restore);
+
 /*----------------------------------------------------------------------------*/
 
 static int __init omap_init_dma(void)

index 54fe966..f1f588a 100644
@@ -528,6 +528,9 @@ extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
 extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
 extern int omap_get_dma_index(int lch, int *ei, int *fi);
 
+void omap_dma_global_context_save(void);
+void omap_dma_global_context_restore(void);
+
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
 extern int omap_request_dma_chain(int dev_id, const char *dev_name,

index c89de1e..386e6c6 100644
@@ -31,6 +31,7 @@
 #include <mach/powerdomain.h>
 
 #include <mach/pm.h>
+#include "prm-regbits-34xx.h"
 #include "pm.h"
 
 unsigned short enable_dyn_sleep;

@@ -87,9 +88,16 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 		gpio_clocks_off_while_idle = value;
 	else if (attr == &uart_clocks_off_while_idle_attr)
 		uart_clocks_off_while_idle = value;
-	else if (attr == &voltage_off_while_idle_attr)
+	else if (attr == &voltage_off_while_idle_attr) {
 		voltage_off_while_idle = value;
-	else
+		if (voltage_off_while_idle)
+			prm_set_mod_reg_bits(OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
+					OMAP3_PRM_VOLTCTRL_OFFSET);
+		else
+			prm_clear_mod_reg_bits(OMAP3430_SEL_OFF,
+					OMAP3430_GR_MOD,
+					OMAP3_PRM_VOLTCTRL_OFFSET);
+	} else
 		return -EINVAL;
 
 	return n;

index 0267959..5242ba0 100644
@@ -297,6 +297,9 @@ void omap_sram_idle(void)
 			omap_serial_enable_clocks(0, 2);
 		}
 		if (core_next_state == PWRDM_POWER_OFF) {
+			prm_set_mod_reg_bits(OMAP3430_AUTO_OFF,
+					OMAP3430_GR_MOD,
+					OMAP3_PRM_VOLTCTRL_OFFSET);
 			omap3_save_core_ctx();
 			omap3_save_prcm_ctx();
 			omap_save_uart_ctx(0);

@@ -334,6 +337,10 @@ void omap_sram_idle(void)
 			omap_restore_uart_ctx(0);
 			omap_restore_uart_ctx(1);
 		}
+		if (core_next_state == PWRDM_POWER_OFF)
+			prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
+					OMAP3430_GR_MOD,
+					OMAP3_PRM_VOLTCTRL_OFFSET);
 		if (per_next_state < PWRDM_POWER_ON) {
 			per_gpio_clk_enable();
 			/* This would be actually more effective */