PCI code: why need outb (0x01, 0xCFB); ?
Quoted 18 lines · Maciej W. Rozycki
Quoted 10 lines · Petr Vandrovec
Quoted 3 lines
Quoted 1 line
1. which device is at port address
0xCFB?Hopefully none.
Actually I'm not sure. This code is here since at least 2.0.28, and during googling I even found code for direct PCI access
(http://www-user.tu-chemnitz.de/~heha/viewzip.cgi/hs_freeware/gerald.zip/DIRECTNT.CPP?auto=CPP)
which sets lowest bit at0xCFBto 1 before doing PCI config accesses and reset it back to original value afterward.Quoted 5 lines
So I believe that there were some chipsets (probably in 486&PCI times) which did conf1/conf2 accesses depending on value of this bit. Unfortunately I was not able to confirm this - almost nobody provides northbridge datasheets from '94 era, even Intel does not provide them (f.e. Neptune) anymore :-(
Quoted 5 lines
Fortunately that's not true. Grab the relevant docs from:
'ftp://download.intel.com/support/chipsets/430nx/'. The semantics of0xcf8,0xcf9,0xcfaand0xcfbI/O ports when used as byte quantities is explained there. Note that0xcf8and0xcfaare the way to get at the PCI config space using conf2 accesses.
Thanks, page 34 of 290479.pdf is exactly what I was looking for (i.e. write 1 to 0xCFB to get PCI conf1, write 0 to get PCI conf2). Next time I'll complain immediately instead of spending time with browsing Intel website and google.
Thanks,
Petr Vandrovec [email protected]
Quoted 10 lines · Petr Vandrovec
Quoted 5 lines
Fortunately that's not true. Grab the relevant docs from:
'ftp://download.intel.com/support/chipsets/430nx/'. The semantics of0xcf8,0xcf9,0xcfaand0xcfbI/O ports when used as byte quantities is explained there. Note that0xcf8and0xcfaare the way to get at the PCI config space using conf2 accesses.Thanks, page 34 of 290479.pdf is exactly what I was looking for (i.e. write 1 to
0xCFBto get PCI conf1, write 0 to get PCI conf2). Next time I'll complain immediately instead of spending time with browsing Intel website and google.
Well, the download.intel.com docs are sometimes hard to get by. There
are a few EISA and basic peripheral specs nearby, too.
Signature · 3 lines
+ Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: [email protected], PGP key available +