ARM: OMAP3: Fix get_irqnr_and_base to clear spurious interrupt bits

@@ -66,7 +66,8 @@
 #endif
 
 #define INTCPS_SIR_IRQ_OFFSET	0x0040		/* Active interrupt offset */
-#define	ACTIVEIRQ_MASK		0x7f		/* Active interrupt bits */
+#define INTCPS_CONTROL		0x0048		/* new interrupt agreement bits */
+#define INTCPS_CONTROL_NEWIRQAGR 0x0001		/* Reset IRQ output and enable new IRQ generation */
 
 		.macro	disable_fiq
 		.endm

@@ -79,18 +80,13 @@
 
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 		ldr	\base, =OMAP2_VA_IC_BASE
-		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-		cmp	\irqnr, #0x0
-		bne	2222f
-		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-		cmp	\irqnr, #0x0
-		bne	2222f
-		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-		cmp	\irqnr, #0x0
+		ldr	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]  /* NOTE: range is 0-0x5f and 0ffffff80 to 0xffffffdf */
+		adds	\tmp, \irqnr, #1 /* change from zero based to 1 based so we clear Z */
+		bpl	2222f  /* if no spurious interrupt */
+		mov	\tmp, #INTCPS_CONTROL_NEWIRQAGR /* Ack the spurious irq */
+		str	\tmp, [\base, #INTCPS_CONTROL]
+		movw	\irqnr, #NR_IRQS /* set to NR_IRQS so that bad_irq_desc() get's called */
 2222:
-		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-		and	\irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-
 		.endm
 
 		.macro	irq_prio_table