64-bit Data Flash Access Problem [MPC8245]
Hi
I have a set of 8 1GB data flash chips (Samsung) on an MPC8245 Ref. Board. These are on a 64-bit bus-mode.
-------DBUS_SIZ[0-1]:DBUS_SIZ[2] = 110b -------
All 8 chips are selected by a single chip select (RCS1). Trying a 32-bit read from the Data Address Location after giving the Command to Access the flash IDs, only 4 flashes on a common byte lane seem to be responding. 32-bit writes appear only on the DH[0-31] and not on DL[0-31].
I am not very clear as to:
(a) How do we perform writes to send out data out on all 64-bits of the bus..?
(b) How would we ideally access 64-bit data through 32- bit reads..?
(c) Or must we *have* 64- bit read/write instructions..?
many thanks in advance for any response ..
Regards
Nebu
Need a new email address that people can remember
Check out the new EudoraMail at
http://www.eudoramail.com
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Quoted 7 lines · Augustine Nebu Philips
I am not very clear as to:
(a) How do we perform writes to send out data out on all 64-bits of the bus..?
(b) How would we ideally access 64-bit data through 32- bit reads..?
(c) Or must we *have* 64- bit read/write instructions..?
This has been discussed before and you can probably find more details in the mailing list archives. There are two approaches. One is to use floating point registers, another is to use cache line operations. Floating point isn't enabled in the kernel, so you will have to make some modifications to context switching if you choose that mode (not my recommendation). You can use the cache line instructions to zero/load/store cache lines that represent I/O to the flash parts. The best solution is to not use 64-bit wide flash arrays....
If you write a user space application and mmap() the flash, which is a common method, either solution is available to you.
good luck.
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/