perf events HW enablement fixes
Subsystems (2)
Linus,
Please pull the latest perf/urgent git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-urgent-2023-01-12
# HEAD: 5268a2842066c227e6ccd94bac562f1e1000244f perf/x86/intel/uncore: Add Emerald Rapids
- More hardware-enablement for Intel Meteor Lake & Emerald Rapid systems:
pure model ID enumeration additions that do not affect other systems.
NOTE: Sending this as an RFC as it's trivial hardware-enablement. Feel free to
skip this & we'll merge it into the -next stream of perf commits. No other fixes are mixed into this tree.
Thanks,
Ingo
------------------>
Kan Liang (4):
perf/x86/cstate: Add Meteor Lake support
perf/x86/msr: Add Meteor Lake support
perf/x86/msr: Add Emerald Rapids
perf/x86/intel/uncore: Add Emerald Rapids
arch/x86/events/intel/cstate.c | 21 ++++++++++++--------- arch/x86/events/intel/uncore.c | 1 + arch/x86/events/msr.c | 3 +++ 3 files changed, 16 insertions(+), 9 deletions(-)
arch/x86/events/intel/cstate.c +12 -9
@@ -41,6 +41,7 @@* MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL +* MTL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01
@@ -51,50 +52,50 @@* perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, -* TGL,TNT,RKL,ADL,RPL,SPR +* TGL,TNT,RKL,ADL,RPL,SPR,MTL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, -* ICL,TGL,RKL,ADL,RPL +* ICL,TGL,RKL,ADL,RPL,MTL * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, -* RPL,SPR +* RPL,SPR,MTL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL, -* ADL,RPL +* ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, -* TGL,TNT,RKL,ADL,RPL,SPR +* TGL,TNT,RKL,ADL,RPL,SPR,MTL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, -* KBL,CML,ICL,TGL,RKL,ADL,RPL +* KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. * perf code: 0x04 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, -* ADL,RPL +* ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. * perf code: 0x05 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, -* ADL,RPL +* ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, -* TNT,RKL,ADL,RPL +* TNT,RKL,ADL,RPL,MTL * Scope: Package (physical package) * */
@@ -686,6 +687,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE , &adl_cstates),X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE_P , &adl_cstates),X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE_S , &adl_cstates), +X86_MATCH_INTEL_FAM6_MODEL (METEORLAKE , &adl_cstates), +X86_MATCH_INTEL_FAM6_MODEL (METEORLAKE_L , &adl_cstates), { }, };MODULE_DEVICE_TABLE (x86cpu, intel_cstates_match);
arch/x86/events/intel/uncore.c +1 -0
@@ -1833,6 +1833,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE_P , &adl_uncore_init),X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE_S , &adl_uncore_init),X86_MATCH_INTEL_FAM6_MODEL (SAPPHIRERAPIDS_X , &spr_uncore_init), +X86_MATCH_INTEL_FAM6_MODEL (EMERALDRAPIDS_X , &spr_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init), {}, };
arch/x86/events/msr.c +3 -0
@@ -69,6 +69,7 @@ static bool test_intel(int idx, void *data)case INTEL_FAM6_BROADWELL_G :case INTEL_FAM6_BROADWELL_X :case INTEL_FAM6_SAPPHIRERAPIDS_X : +case INTEL_FAM6_EMERALDRAPIDS_X :case INTEL_FAM6_ATOM_SILVERMONT :case INTEL_FAM6_ATOM_SILVERMONT_D :
@@ -107,6 +108,8 @@ static bool test_intel(int idx, void *data)case INTEL_FAM6_RAPTORLAKE :case INTEL_FAM6_RAPTORLAKE_P :case INTEL_FAM6_RAPTORLAKE_S : +case INTEL_FAM6_METEORLAKE : +case INTEL_FAM6_METEORLAKE_L :if (idx ==PERF_MSR_SMI || idx ==PERF_MSR_PPERF )return true;break ;