net: dsa: always use phylink
Subsystems (15)
Russell King (Oracle)
maintainercover net: dsa: always use phylink
Mostly the same as the previous RFC, except:
1) incldues the phylink_validate_mask_caps() function
2) has Marek's idea of searching the supported_interfaces bitmap for the fastest interface we can use
3) includes a final patch to add a print which will be useful to hear from people testing it.
Some of the questions from the original RFC remain though, so I've included that text below. I'm guessing as they remain unanswered that no one has any opinions on them?
drivers/net/dsa/b53/b53_common.c | 3 +- drivers/net/dsa/bcm_sf2.c | 3 +- drivers/net/dsa/hirschmann/hellcreek.c | 3 +- drivers/net/dsa/lantiq_gswip.c | 6 +- drivers/net/dsa/microchip/ksz_common.c | 3 +- drivers/net/dsa/mt7530.c | 3 +- drivers/net/dsa/mv88e6xxx/chip.c | 53 ++++-------- drivers/net/dsa/ocelot/felix.c | 3 +- drivers/net/dsa/qca/ar9331.c | 3 +- drivers/net/dsa/qca8k.c | 3 +- drivers/net/dsa/realtek/rtl8365mb.c | 3 +- drivers/net/dsa/sja1105/sja1105_main.c | 3 +- drivers/net/dsa/xrs700x/xrs700x.c | 3 +- drivers/net/phy/phylink.c | 148 ++++++++++++++++++++++++++++++--- include/linux/phylink.h | 5 ++ include/net/dsa.h | 3 +- net/dsa/port.c | 47 +++++++---- 17 files changed, 215 insertions(+), 80 deletions(-)
Quoted 65 lines · Russell King (Oracle)
Hi,
Currently, the core DSA code conditionally uses phylink for CPU and DSA ports depending on whether the firmware specifies a fixed-link or a PHY. If either of these are specified, then phylink is used for these ports, otherwise phylink is not, and we rely on the DSA drivers to "do the right thing". However, this detail is not mentioned in the DT binding, but Andrew has said that this behaviour has always something that DSA wants.
mv88e6xxx has had support for this for a long time with its "
SPEED_MAX" thing, which I recently reworked to make use of themac_capabilitiesin preparation to solving this more fully.This series is an experiment to solve this properly, and it does this in two steps.
The first step consists of the first two patches. Phylink needs to know the PHY interface mode that is being used so it can (a) pass the right mode into the MAC/PCS etc and (b) know the properties of the link and therefore which speeds can be supported across it.
In order to achieve this, the DSA
phylink_get_caps()method has an extra argument added to it so that DSA drivers can report the interface mode that they will be using for this port back to the core DSA code, thereby allowing phylink to be initialised with the correct interface mode.Note that this can only be used for CPU and DSA ports as "user" ports need a different behaviour - they rely on getting the interface mode from phylib, which will only happen if phylink is initialised with
PHY_INTERFACE_MODE_NA. Unfortunately, changing this behaviour is likely to cause widespread regressions.Obvious questions:
1. Shouldphylink_get_caps()be augmented in this way, or should it be a separate method?2. DSA has traditionally used "interface mode for the maximum supported speed on this port" where the interface mode is programmable (via its internal
port_max_speed_mode()method) but this is only present for a few of the sub-drivers. Is reporting the current interface mode correct where this method is not implemented?The second step is to introduce a function that allows phylink to be reconfigured after creation time to operate at max-speed fixed-link mode for the PHY interface mode, also using the MAC capabilities to determine the speed and duplex mode we should be using.
Obvious questions:
1. Should we be allowing half-duplex for this?
2. If we do allow half-duplex, should we prefer fastest speed over duplex setting, or should we prefer fastest full-duplex speed over any half-duplex?
3. How do we sanely switch DSA from its current behaviour to always using phylink for these ports without breakage - this is the difficult one, because it's not obvious which drivers have been coded to either work around this quirk of the DSA implementation. For example, if we start forcing the link down before callingdsa_port_phylink_create(), and we then fail to set max-fixed-link, then the CPU/DSA port is going to fail, and we're going to have lots of regressions.Please look at the patches and make suggestions on how we can proceed to clean up this quirk of DSA.
Signature · 2 lines
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
RFC PATCH 1/6 net: dsa: add support for retrieving the interface mode
DSA port bindings allow for an optional phy interface mode. When an interface mode is not specified, DSA uses the NA interface mode type.
However, phylink needs to know the parameters of the link, and this will become especially important when using phylink for ports that are devoid of all properties except the required "reg" property, so that phylink can select the maximum supported link settings. Without knowing the interface mode, phylink can't truely know the maximum link speed.
Update the prototype for the phylink_get_caps method to allow drivers to report this information back to DSA, and update all DSA implementations function declarations to cater for this change. No code is added to the implementations.
--- drivers/net/dsa/b53/b53_common.c | 3 ++- drivers/net/dsa/bcm_sf2.c | 3 ++- drivers/net/dsa/hirschmann/hellcreek.c | 3 ++- drivers/net/dsa/lantiq_gswip.c | 6 ++++-- drivers/net/dsa/microchip/ksz_common.c | 3 ++- drivers/net/dsa/mt7530.c | 3 ++- drivers/net/dsa/mv88e6xxx/chip.c | 3 ++- drivers/net/dsa/ocelot/felix.c | 3 ++- drivers/net/dsa/qca/ar9331.c | 3 ++- drivers/net/dsa/qca8k.c | 3 ++- drivers/net/dsa/realtek/rtl8365mb.c | 3 ++- drivers/net/dsa/sja1105/sja1105_main.c | 3 ++- drivers/net/dsa/xrs700x/xrs700x.c | 3 ++- include/net/dsa.h | 3 ++- net/dsa/port.c | 23 +++++++++++++++++------ 15 files changed, 47 insertions(+), 21 deletions(-)
drivers/net/dsa/b53/b53_common.c +2 -1
@@ -1310,7 +1310,8 @@ void b53_port_event(struct dsa_switch *ds, int port)EXPORT_SYMBOL (b53_port_event);static void b53_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {struct b53_device *dev = ds->priv;
drivers/net/dsa/bcm_sf2.c +2 -1
@@ -713,7 +713,8 @@ static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) }static void bcm_sf2_sw_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {unsigned long *interfaces = config->supported_interfaces;struct bcm_sf2_priv *priv =bcm_sf2_to_priv (ds);
drivers/net/dsa/hirschmann/hellcreek.c +2 -1
@@ -1462,7 +1462,8 @@ static void hellcreek_teardown(struct dsa_switch *ds) }static void hellcreek_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {struct hellcreek *hellcreek = ds->priv;
drivers/net/dsa/lantiq_gswip.c +4 -2
@@ -1492,7 +1492,8 @@ static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) }static void gswip_xrx200_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {switch (port) {case 0 :
@@ -1525,7 +1526,8 @@ static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port, }static void gswip_xrx300_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {switch (port) {case 0 :
drivers/net/dsa/microchip/ksz_common.c +2 -1
@@ -560,7 +560,8 @@ static int ksz_check_device_id(struct ksz_device *dev) }static void ksz_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {struct ksz_device *dev = ds->priv;
drivers/net/dsa/mt7530.c +2 -1
@@ -2914,7 +2914,8 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port) }static void mt753x_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {struct mt7530_priv *priv = ds->priv;
drivers/net/dsa/mv88e6xxx/chip.c +2 -1
@@ -819,7 +819,8 @@ static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, }static void mv88e6xxx_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {struct mv88e6xxx_chip *chip = ds->priv;
drivers/net/dsa/ocelot/felix.c +2 -1
@@ -937,7 +937,8 @@ static int felix_vlan_del(struct dsa_switch *ds, int port, }static void felix_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {struct ocelot *ocelot = ds->priv;
drivers/net/dsa/qca/ar9331.c +2 -1
@@ -500,7 +500,8 @@ static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds, }static void ar9331_sw_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) { config->mac_capabilities =MAC_ASYM_PAUSE |MAC_SYM_PAUSE |MAC_10 |MAC_100 ;
drivers/net/dsa/qca8k.c +2 -1
@@ -1749,7 +1749,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, }static void qca8k_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {switch (port) {case 0 :/* 1st CPU port */
drivers/net/dsa/realtek/rtl8365mb.c +2 -1
@@ -1024,7 +1024,8 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, }static void rtl8365mb_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {const struct rtl8365mb_extint *extint =rtl8365mb_get_port_extint (ds->priv, port);
drivers/net/dsa/sja1105/sja1105_main.c +2 -1
@@ -1390,7 +1390,8 @@ static void sja1105_mac_link_up(struct dsa_switch *ds, int port, }static void sja1105_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {struct sja1105_private *priv = ds->priv;struct sja1105_xmii_params_entry *mii;
drivers/net/dsa/xrs700x/xrs700x.c +2 -1
@@ -443,7 +443,8 @@ static void xrs700x_teardown(struct dsa_switch *ds) }static void xrs700x_phylink_get_caps (struct dsa_switch *ds,int port, -struct phylink_config *config) +struct phylink_config *config, +phy_interface_t *default_interface) {switch (port) {case 0 :
include/net/dsa.h +2 -1
@@ -850,7 +850,8 @@ struct dsa_switch_ops {* PHYLINK integration */ void (*phylink_get_caps)(struct dsa_switch *ds,int port, -struct phylink_config *config); +struct phylink_config *config, +phy_interface_t *default_interface);void (*phylink_validate)(struct dsa_switch *ds,int port,unsigned long *supported,struct phylink_link_state *state);
net/dsa/port.c +17 -6
@@ -1524,13 +1524,9 @@ static const struct phylink_mac_ops dsa_port_phylink_mac_ops = {int dsa_port_phylink_create (struct dsa_port *dp) {struct dsa_switch *ds = dp->ds; -phy_interface_t mode; +phy_interface_t mode, def_mode;int err; - err =of_get_phy_mode (dp->dn, &mode); -if (err) - mode =PHY_INTERFACE_MODE_NA ; -/* Presence of phylink_mac_link_state or phylink_mac_an_restart is * an indicator of a legacy phylink driver. */
@@ -1538,8 +1534,23 @@ int dsa_port_phylink_create(struct dsa_port *dp) ds->ops->phylink_mac_an_restart) dp->pl_config.legacy_pre_march2020 = true; + def_mode =PHY_INTERFACE_MODE_NA ;if (ds->ops->phylink_get_caps) - ds->ops->phylink_get_caps (ds, dp->index, &dp->pl_config); + ds->ops->phylink_get_caps (ds, dp->index, &dp->pl_config, + &def_mode); + + err =of_get_phy_mode (dp->dn, &mode); +if (err) { +/* We must not set the default mode for user ports as a PHY +* overrides the NA mode in phylink. Setting it here would +* prevent the interface mode being updated. +*/ +if (dp->type ==DSA_PORT_TYPE_CPU || + dp->type ==DSA_PORT_TYPE_DSA ) + mode = def_mode; +else + mode =PHY_INTERFACE_MODE_NA ; + } dp->pl =phylink_create (&dp->pl_config,of_fwnode_handle (dp->dn), mode, &dsa_port_phylink_mac_ops);
Signature · 1 line
2.30.2
RFC PATCH 2/6 net: dsa: mv88e6xxx: report the default interface mode for the port
In reply to Russell King (Oracle)Report the maximum speed interface mode for the port, or if we don't have that information, the hardware configured interface mode for the port.
This allows phylink to know which interface mode CPU and DSA ports are operating, which will be necessary when we want to select the maximum speed for the port (required for such ports without a PHY or fixed-link specified in firmware.)
--- drivers/net/dsa/mv88e6xxx/chip.c | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/net/dsa/mv88e6xxx/chip.c +9 -0
@@ -823,6 +823,7 @@ static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, phy_interface_t *default_interface) {struct mv88e6xxx_chip *chip = ds->priv; +u8 cmode = chip->ports[port].cmode; chip->info->ops->phylink_get_caps (chip, port, config);
@@ -830,6 +831,14 @@ static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,if (mv88e6xxx_phy_is_internal (ds, port))__set_bit (PHY_INTERFACE_MODE_GMII , config->supported_interfaces); + +if (chip->info->ops->port_max_speed_mode) + *default_interface = chip->info->ops->port_max_speed_mode (port); +else if (cmode <ARRAY_SIZE (mv88e6xxx_phy_interface_modes) && + mv88e6xxx_phy_interface_modes[cmode]) + *default_interface = mv88e6xxx_phy_interface_modes[cmode]; +else if (cmode ==MV88E6XXX_PORT_STS_CMODE_RGMII ) + *default_interface =PHY_INTERFACE_MODE_RGMII ; } static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
Signature · 1 line
2.30.2
RFC PATCH 3/6 net: phylink: split out interface to caps translation
In reply to Russell King (Oracle)phylink_get_linkmodes() translates the interface mode into a set of speed and duplex capabilities which are masked with the MAC modes to then derive the link modes that are available.
Split out the initial transformation into a new function phylink_interface_to_caps(), which will be useful when setting the maximum fixed link speed.
--- drivers/net/phy/phylink.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-)
drivers/net/phy/phylink.c +19 -12
@@ -296,18 +296,7 @@ static void phylink_caps_to_linkmodes(unsigned long *linkmodes, } } -/** -* phylink_get_linkmodes() - get acceptable link modes -* @linkmodes: ethtool linkmode mask (must be already initialised) -* @interface: phy interface mode defined by &typedef phy_interface_t -* @mac_capabilities: bitmask of MAC capabilities -* -* Set all possible pause, speed and duplex linkmodes in @linkmodes that -* are supported by the @interface mode and @mac_capabilities. @linkmodes -* must have been initialised previously. -*/ -void phylink_get_linkmodes (unsigned long *linkmodes,phy_interface_t interface, -unsigned long mac_capabilities) +static unsigned long phylink_interface_to_caps (phy_interface_t interface) {unsigned long caps =MAC_SYM_PAUSE |MAC_ASYM_PAUSE ;
@@ -381,6 +370,24 @@ void phylink_get_linkmodes(unsigned long *linkmodes, phy_interface_t interface,break ; } +return caps; +} + +/** +* phylink_get_linkmodes() - get acceptable link modes +* @linkmodes: ethtool linkmode mask (must be already initialised) +* @interface: phy interface mode defined by &typedef phy_interface_t +* @mac_capabilities: bitmask of MAC capabilities +* +* Set all possible pause, speed and duplex linkmodes in @linkmodes that +* are supported by the @interface mode and @mac_capabilities. @linkmodes +* must have been initialised previously. +*/ +void phylink_get_linkmodes (unsigned long *linkmodes,phy_interface_t interface, +unsigned long mac_capabilities) +{ +unsigned long caps =phylink_interface_to_caps (interface); +phylink_caps_to_linkmodes (linkmodes, caps & mac_capabilities); }EXPORT_SYMBOL_GPL (phylink_get_linkmodes);
Signature · 1 line
2.30.2
RFC PATCH 4/6 net: phylink: add phylink_set_max_fixed_link()
In reply to Russell King (Oracle)Add a function for DSA to use to configure phylink, in the absence of any other configuration, to a fixed link operating at the maximum supported link speed.
This is needed so we can support phylink usage on CPU and DSA ports.
--- drivers/net/phy/phylink.c | 110 ++++++++++++++++++++++++++++++++++++++ include/linux/phylink.h | 5 ++ 2 files changed, 115 insertions(+)
drivers/net/phy/phylink.c +110 -0
@@ -1333,6 +1333,116 @@ void phylink_destroy(struct phylink *pl) }EXPORT_SYMBOL_GPL (phylink_destroy); +static struct { +unsigned long fd_mask; +unsigned long hd_mask; +int speed; +} phylink_caps_speeds[] = { + {MAC_400000FD ,0 ,SPEED_400000 }, + {MAC_200000FD ,0 ,SPEED_200000 }, + {MAC_100000FD ,0 ,SPEED_100000 }, + {MAC_56000FD ,0 ,SPEED_56000 }, + {MAC_50000FD ,0 ,SPEED_50000 }, + {MAC_40000FD ,0 ,SPEED_40000 }, + {MAC_25000FD ,0 ,SPEED_40000 }, + {MAC_20000FD ,0 ,SPEED_20000 }, + {MAC_10000FD ,0 ,SPEED_10000 }, + {MAC_5000FD ,0 ,SPEED_5000 }, + {MAC_2500FD ,0 ,SPEED_2500 }, + {MAC_1000FD ,MAC_1000HD ,SPEED_1000 }, + {MAC_100FD ,MAC_100HD ,SPEED_100 }, + {MAC_10FD ,MAC_10HD ,SPEED_10 }, +}; + +/** +* phylink_set_max_fixed_link() - set a fixed link configuration for phylink +* @pl: a pointer to a &struct phylink returned from phylink_create() +* +* Set a maximum speed fixed-link configuration for the chosen interface +* mode and MAC capabilities for the phylink instance. Only valid for use +* immediately after creation. Must not be used at any other time. +* +* The user must have initialised mac_capabilities and set a valid interface. +*/ +int phylink_set_max_fixed_link (struct phylink *pl) +{ +phy_interface_t intf, interface; +unsigned long caps, max_caps; +unsigned long *interfaces; +int speed, duplex; +int i; + +/* If we are not in PHY mode, or have a PHY, or have a SFP bus, +* then we must not default to a fixed link. +*/ +if (pl->cfg_link_an_mode !=MLO_AN_PHY || pl->phydev || pl->sfp_bus) +return -EBUSY ; + + interface = pl->link_interface; +if (interface !=PHY_INTERFACE_MODE_NA ) { +/* Get the speed/duplex capabilities and reduce according to the +* specified interface mode. +*/ + caps = pl->config->mac_capabilities; + caps &=phylink_interface_to_caps (interface); + }else { + interfaces = pl->config->supported_interfaces; + max_caps =0 ; + +/* Find the supported interface mode which gives the maximum +* speed. +*/ +for (intf =0 ; intf <PHY_INTERFACE_MODE_MAX ; intf++) { +if (test_bit (intf, interfaces)) { + caps = pl->config->mac_capabilities; + caps &=phylink_interface_to_caps (intf); +if (caps > max_caps) { + max_caps = caps; + interface = intf; + } + } + } + + caps = max_caps; + } + + caps &= ~(MAC_SYM_PAUSE |MAC_ASYM_PAUSE ); + +/* If there are no capabilities, then we are not using this default. */ +if (!caps) +return -EINVAL ; + +/* Decode to fastest speed and duplex */ + duplex =DUPLEX_UNKNOWN ; + speed =SPEED_UNKNOWN ; +for (i =0 ; i <ARRAY_SIZE (phylink_caps_speeds); i++) { +if (caps & phylink_caps_speeds[i].fd_mask) { + duplex =DUPLEX_FULL ; + speed = phylink_caps_speeds[i].speed; +break ; + }else if (caps & phylink_caps_speeds[i].hd_mask) { + duplex =DUPLEX_HALF ; + speed = phylink_caps_speeds[i].speed; +break ; + } + } + +/* If we didn't find anything, bail. */ +if (speed ==SPEED_UNKNOWN ) +return -EINVAL ; + + pl->link_interface = interface; + pl->link_config.interface = interface; + pl->link_config.speed = speed; + pl->link_config.duplex = duplex; + pl->link_config.link =1 ; + pl->cfg_link_an_mode =MLO_AN_FIXED ; + pl->cur_link_an_mode =MLO_AN_FIXED ; + +return 0 ; +} +EXPORT_SYMBOL_GPL (phylink_set_max_fixed_link); +static void phylink_phy_change (struct phy_device *phydev,bool up) {struct phylink *pl = phydev->phylink;
include/linux/phylink.h +5 -0
@@ -23,6 +23,9 @@ enum {MAC_SYM_PAUSE =BIT (0 ),MAC_ASYM_PAUSE =BIT (1 ), +/* These speed bits must be sorted according to speed for +* phylink_set_max_fixed_link() +*/ MAC_10HD =BIT (2 ),MAC_10FD =BIT (3 ), MAC_10 = MAC_10HD | MAC_10FD,
@@ -529,6 +532,8 @@ struct phylink *phylink_create(struct phylink_config *, struct fwnode_handle *, const struct phylink_mac_ops *mac_ops);void phylink_destroy (struct phylink *); +int phylink_set_max_fixed_link (struct phylink *pl); +int phylink_connect_phy (struct phylink *,struct phy_device *);int phylink_of_phy_connect (struct phylink *,struct device_node *,u32 flags); int phylink_fwnode_phy_connect(struct phylink *pl,
Signature · 1 line
2.30.2
RFC PATCH 5/6 net: dsa: always use phylink for CPU and DSA ports
In reply to Russell King (Oracle)Currently, we only use phylink for CPU and DSA ports if there is a fixed-link specification, or a PHY specified. The reason for this behaviour is that when neither is specified, there was no way for phylink to know the link parameters.
Now that we have phylink_set_max_link_speed() (which has become possible through the addition of mac_capabilities) we now have the ability to know the maximum link speed for a specific link, and can now use phylink for this case as well.
However, we need DSA drivers to report the interface mode being used on these ports so that we can select a maximum speed appropriate for the interface mode that hardware may have configured for the port.
This is especially important with the conversion of DSA drivers to phylink_pcs, as the PCS code only gets called if we are using phylink for the port.
--- drivers/net/dsa/mv88e6xxx/chip.c | 41 ++++---------------------------- net/dsa/port.c | 24 ++++++++++--------- 2 files changed, 18 insertions(+), 47 deletions(-)
drivers/net/dsa/mv88e6xxx/chip.c +5 -36
@@ -3287,9 +3287,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) {struct device_node *phy_handle =NULL ;struct dsa_switch *ds = chip->ds; -phy_interface_t mode;struct dsa_port *dp; -int tx_amp, speed; +int tx_amp;int err;u16 reg;
@@ -3298,40 +3297,10 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) dp =dsa_to_port (ds, port); -/* MAC Forcing register: don't force link, speed, duplex or flow control -* state to any particular values on physical ports, but force the CPU -* port and all DSA ports to their maximum bandwidth and full duplex. -*/ -if (dsa_is_cpu_port (ds, port) ||dsa_is_dsa_port (ds, port)) { -unsigned long caps = dp->pl_config.mac_capabilities; - -if (chip->info->ops->port_max_speed_mode) - mode = chip->info->ops->port_max_speed_mode (port); -else - mode =PHY_INTERFACE_MODE_NA ; - -if (caps &MAC_10000FD ) - speed =SPEED_10000 ; -else if (caps &MAC_5000FD ) - speed =SPEED_5000 ; -else if (caps &MAC_2500FD ) - speed =SPEED_2500 ; -else if (caps &MAC_1000 ) - speed =SPEED_1000 ; -else if (caps &MAC_100 ) - speed =SPEED_100 ; -else - speed =SPEED_10 ; - - err =mv88e6xxx_port_setup_mac (chip, port,LINK_FORCED_UP , - speed,DUPLEX_FULL , -PAUSE_OFF , mode); - }else { - err =mv88e6xxx_port_setup_mac (chip, port,LINK_UNFORCED , -SPEED_UNFORCED ,DUPLEX_UNFORCED , -PAUSE_ON , -PHY_INTERFACE_MODE_NA ); - } + err =mv88e6xxx_port_setup_mac (chip, port,LINK_UNFORCED , +SPEED_UNFORCED ,DUPLEX_UNFORCED , +PAUSE_ON , +PHY_INTERFACE_MODE_NA );if (err)return err;
net/dsa/port.c +13 -11
@@ -1525,6 +1525,7 @@ int dsa_port_phylink_create(struct dsa_port *dp) {struct dsa_switch *ds = dp->ds;phy_interface_t mode, def_mode; +struct device_node *phy_np;int err;/* Presence of phylink_mac_link_state or phylink_mac_an_restart is
@@ -1559,6 +1560,13 @@ int dsa_port_phylink_create(struct dsa_port *dp)return PTR_ERR (dp->pl); } +if (dp->type ==DSA_PORT_TYPE_CPU || dp->type ==DSA_PORT_TYPE_DSA ) { + phy_np =of_parse_phandle (dp->dn,"phy-handle" ,0 ); +of_node_put (phy_np); +if (!phy_np) + err =phylink_set_max_fixed_link (dp->pl); + } +return 0 ; }
@@ -1663,20 +1671,14 @@ static int dsa_port_phylink_register(struct dsa_port *dp)int dsa_port_link_register_of (struct dsa_port *dp) {struct dsa_switch *ds = dp->ds; -struct device_node *phy_np;int port = dp->index;if (!ds->ops->adjust_link) { - phy_np =of_parse_phandle (dp->dn,"phy-handle" ,0 ); -if (of_phy_is_fixed_link (dp->dn) || phy_np) { -if (ds->ops->phylink_mac_link_down) - ds->ops->phylink_mac_link_down (ds, port, -MLO_AN_FIXED ,PHY_INTERFACE_MODE_NA ); -of_node_put (phy_np); -return dsa_port_phylink_register (dp); - } -of_node_put (phy_np); -return 0 ; +if (ds->ops->phylink_mac_link_down) + ds->ops->phylink_mac_link_down (ds, port, +MLO_AN_FIXED ,PHY_INTERFACE_MODE_NA ); + +return dsa_port_phylink_register (dp); } dev_warn(ds->dev,
Signature · 1 line
2.30.2
RFC PATCH 6/6 net: phylink: debug print
In reply to Russell King (Oracle)--- drivers/net/phy/phylink.c | 7 +++++++ 1 file changed, 7 insertions(+)
drivers/net/phy/phylink.c +7 -0
@@ -1378,6 +1378,13 @@ int phylink_set_max_fixed_link(struct phylink *pl)if (pl->cfg_link_an_mode !=MLO_AN_PHY || pl->phydev || pl->sfp_bus)return -EBUSY ; +phylink_info (pl,"sif=%*pbl if=%d(%s) cap=%lx\n" , + (int )PHY_INTERFACE_MODE_MAX , + pl->config->supported_interfaces, + pl->link_interface, +phy_modes (pl->link_interface), + pl->config->mac_capabilities); + interface = pl->link_interface;if (interface !=PHY_INTERFACE_MODE_NA ) {/* Get the speed/duplex capabilities and reduce according to the
Signature · 1 line
2.30.2
Re: [PATCH RFC net-next 1/6] net: dsa: add support for retrieving the interface mode
In reply to Russell King (Oracle)Quoted 10 lines · On Wed, 29 Jun 2022 13:51:22 +0100 "Russell King (Oracle)"…
DSA port bindings allow for an optional phy interface mode. When an interface mode is not specified, DSA uses the NA interface mode type.
However, phylink needs to know the parameters of the link, and this will become especially important when using phylink for ports that are devoid of all properties except the required "reg" property, so that phylink can select the maximum supported link settings. Without knowing the interface mode, phylink can't truely know the maximum link speed.
Quoted 6 lines
Update the prototype for the
phylink_get_capsmethod to allow drivers to report this information back to DSA, and update all DSA implementations function declarations to cater for this change. No code is added to the implementations.Signed-off-by Russell King (Oracle) <[email protected]>
Re: [PATCH RFC net-next 2/6] net: dsa: mv88e6xxx: report the default interface mode for the port
In reply to Russell King (Oracle)Quoted 28 lines · On Wed, 29 Jun 2022 13:51:27 +0100 "Russell King (Oracle)"…
Report the maximum speed interface mode for the port, or if we don't have that information, the hardware configured interface mode for the port.
This allows phylink to know which interface mode CPU and DSA ports are operating, which will be necessary when we want to select the maximum speed for the port (required for such ports without a PHY or fixed-link specified in firmware.)
Signed-off-by Russell King (Oracle) <[email protected]>--- drivers/net/dsa/mv88e6xxx/chip.c | 9 +++++++++ 1 file changed, 9 insertions(+)drivers/net/dsa/mv88e6xxx/chip.c +1
-0@@ -823,6 +823,7 @@ static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, phy_interface_t *default_interface) {struct mv88e6xxx_chip *chip = ds->priv; +u8 cmode = chip->ports[port].cmode; chip->info->ops->phylink_get_caps (chip, port, config);@@ -830,6 +831,14 @@ static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,if (mv88e6xxx_phy_is_internal (ds, port))
drivers/net/dsa/mv88e6xxx/chip.c static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, · line 841
Quoted 10 lines
drivers/net/dsa/mv88e6xxx/chip.c +8
-0__set_bit (PHY_INTERFACE_MODE_GMII , config->supported_interfaces); + +if (chip->info->ops->port_max_speed_mode) + *default_interface = chip->info->ops->port_max_speed_mode (port); +else if (cmode <ARRAY_SIZE (mv88e6xxx_phy_interface_modes) && + mv88e6xxx_phy_interface_modes[cmode]) + *default_interface = mv88e6xxx_phy_interface_modes[cmode]; +else if (cmode ==MV88E6XXX_PORT_STS_CMODE_RGMII ) + *default_interface =PHY_INTERFACE_MODE_RGMII ;
Will this work correctly for 6185? That one has different array, mv88e6185_phy_interface_modes.
Maybe instead we need to send the default_interface parameter to chip->info->ops->phylink_get_caps() ?
Marek
Re: [PATCH RFC net-next 3/6] net: phylink: split out interface to caps translation
In reply to Russell King (Oracle)Quoted 9 lines · On Wed, 29 Jun 2022 13:51:33 +0100 "Russell King (Oracle)"…
phylink_get_linkmodes()translates the interface mode into a set of speed and duplex capabilities which are masked with the MAC modes to then derive the link modes that are available.Split out the initial transformation into a new function
phylink_interface_to_caps(), which will be useful when setting the maximum fixed link speed.Signed-off-by Russell King (Oracle) <[email protected]>
Re: [PATCH RFC net-next 4/6] net: phylink: add phylink_set_max_fixed_link()
In reply to Russell King (Oracle)Quoted 7 lines · On Wed, 29 Jun 2022 13:51:38 +0100 "Russell King (Oracle)"…
Add a function for DSA to use to configure phylink, in the absence of any other configuration, to a fixed link operating at the maximum supported link speed.
This is needed so we can support phylink usage on CPU and DSA ports.
Signed-off-by Russell King (Oracle) <[email protected]>
Re: [PATCH RFC net-next 5/6] net: dsa: always use phylink for CPU and DSA ports
In reply to Russell King (Oracle)Quoted 14 lines · On Wed, 29 Jun 2022 13:51:43 +0100 "Russell King (Oracle)"…
Currently, we only use phylink for CPU and DSA ports if there is a fixed-link specification, or a PHY specified. The reason for this behaviour is that when neither is specified, there was no way for phylink to know the link parameters.
Now that we have
phylink_set_max_link_speed()(which has become possible through the addition ofmac_capabilities) we now have the ability to know the maximum link speed for a specific link, and can now use phylink for this case as well.However, we need DSA drivers to report the interface mode being used on these ports so that we can select a maximum speed appropriate for the interface mode that hardware may have configured for the port.
Quoted 5 lines
This is especially important with the conversion of DSA drivers to
phylink_pcs, as the PCS code only gets called if we are using phylink for the port.Signed-off-by Russell King (Oracle) <[email protected]>
So this is the one that may break other drivers?
Marek
Russell King (Oracle)
maintainerRe: [PATCH RFC net-next 5/6] net: dsa: always use phylink for CPU and DSA ports
Quoted 21 lines · Marek Behún
Quoted 18 lines · On Wed, 29 Jun 2022 13:51:43 +0100 "Russell King (Oracle)"…
Currently, we only use phylink for CPU and DSA ports if there is a fixed-link specification, or a PHY specified. The reason for this behaviour is that when neither is specified, there was no way for phylink to know the link parameters.
Now that we have
phylink_set_max_link_speed()(which has become possible through the addition ofmac_capabilities) we now have the ability to know the maximum link speed for a specific link, and can now use phylink for this case as well.However, we need DSA drivers to report the interface mode being used on these ports so that we can select a maximum speed appropriate for the interface mode that hardware may have configured for the port.
This is especially important with the conversion of DSA drivers to
phylink_pcs, as the PCS code only gets called if we are using phylink for the port.
Quoted 5 lines
Quoted 1 line
Signed-off-by Russell King (Oracle) <[email protected]>Reviewed-by Marek Behún <[email protected]>So this is the one that may break other drivers?
It's the one that I'm most concerned about breakage happening, because the other drivers won't be setting the default interface for the port, which means if they're taking advantage of this "defaulting" feature, this patch will break them.
The original code just did nothing when this "defaulting" feature was used - it didn't call the DSA phylink_mac_link_down() op, and didn't register with phylink. The phylink_mac_link_down() there was to ensure that the ports are in a link-down state prior to setting up phylink, because that's what phylink expects.
The problem comes is that once we've called phylink_mac_link_down(), there isn't a way to back out of that without knowing the interface mode, speed, duplex etc - which is the problem with this defaulting feature, none of that is specified in DT, it can only come from the drivers.
Note that the mv88e6xxx series I posted earlier depends on getting this problem sorted - if we don't, I can't send the mv88e6xxx pcs conversion because mv88e6xxx boards that _do_ make use of this defaulting feature will break (and there are a number that do make use of it.)
If I send this RFC series (minus the top patch) then all the drivers that make use of this defualting feature that aren't mv88e6xxx will probably break - but I've no idea which make use of this feature because it's not documented. It's not really documented in the DT binding either, it's just something that Andrew "knows about", mv88e6xxx makes use of, and Andrew has suggested to some other DSA driver authors.
This absolutely needs Andrew's involvement.
Signature · 2 lines
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